公开(公告)号：US20220155990A1

公开(公告)日：2022-05-19

申请号：US17419736

申请日：2019-07-31

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Mark A. Piwonka ,  Stanley Hyojun Park ,  Michael R. Durham ,  Ted T. Nguy

IPC: G06F3/06 ,  G06F12/0891 ,  G06F8/654

Abstract: An example non-transitory machine-readable storage medium storing machine-readable instructions which when executed cause a processor to obtain stored bits stored on a flash memory, each of the stored bits in a set state or an unset state. The processor further obtains target bits, each of the target bits in the set state or the unset state, wherein each target bit corresponds to a stored bit to update the stored bit. The processor further determines whether, for one stored bit in the set state, the corresponding target bit is in the unset state. When the determination is positive, the processor sets the stored bits to the unset state and, after setting the stored bits to the unset state, updates the stored bits to match the corresponding target bits. When the determination is negative, the processor updates the stored bits to match the corresponding target bits.

公开(公告)号：US11762575B2

公开(公告)日：2023-09-19

申请号：US17419736

申请日：2019-07-31

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Mark A. Piwonka ,  Stanley Hyojun Park ,  Michael R. Durham ,  Ted T. Nguy

IPC: G06F3/06 ,  G06F8/654 ,  G06F12/0891

CPC classification number: G06F3/0652 ,  G06F3/0608 ,  G06F3/0679 ,  G06F8/654 ,  G06F12/0891 ,  G06F2212/1041 ,  G06F2212/222

Abstract: An example non-transitory machine-readable storage medium storing machine-readable instructions which when executed cause a processor to obtain stored bits stored on a flash memory, each of the stored bits in a set state or an unset state. The processor further obtains target bits, each of the target bits in the set state or the unset state, wherein each target bit corresponds to a stored bit to update the stored bit. The processor further determines whether, for one stored bit in the set state, the corresponding target bit is in the unset state. When the determination is positive, the processor sets the stored bits to the unset state and, after setting the stored bits to the unset state, updates the stored bits to match the corresponding target bits. When the determination is negative, the processor updates the stored bits to match the corresponding target bits.

公开(公告)号：US20220197359A1

公开(公告)日：2022-06-23

申请号：US17606087

申请日：2019-07-30

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Shaheen Saroor ,  Nam Hoang Nguyen ,  Ted T. Nguy

IPC: G06F1/26 ,  G06F1/18 ,  G06F13/40 ,  G06F13/38

Abstract: An example display device includes a universal serial bus interface to couple to a host computing device; and a power delivery controller interconnected with the universal serial bus interface. The power delivery controller is to obtain from a host state register stored at the display device, a current power state of the host computing device responsive to a change in state of the display device from a first power state to a second power state. The power delivery controller is further to send a power delivery protocol message to the host computing device to synchronize a power state of the host computing device to an updated power state corresponding to the second power state when the current power state of the host computing device corresponds to the first power state. The power delivery controller is further to update the host state register to reflect the updated power state.