-
公开(公告)号：US06563755B2
公开(公告)日：2003-05-13
申请号：US09986082
申请日：2001-11-07
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor memory device realizing a reduced cycle time while improving the ease of use is to be provided. Where a memory cell requires a periodic refresh action to hold stored information, a time multiplexing mode of performing, when a first memory operation on any memory cell to read or write stored information or information to be stored and a second memory operation, having a different address designation from the first memory operation, or a refresh operation compete for the same time segment, the second memory operation before or after such first memory operation, wherein the minimum access time needed for the first memory operation and the second memory operation or the refresh operation performed before or after the first memory operation is set shorter than the sum of the length of time required for the first memory operation and that required for the second memory operation or the refresh operation on condition that sets of information stored in the memory cells are not mutually affected in the first memory operation and the second memory operation or the refresh operation.
-
公开(公告)号：US20050073895A1
公开(公告)日：2005-04-07
申请号：US10636558
申请日：2003-08-08
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译： 为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时 发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作， 内存操作后。 伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。
-
公开(公告)号：US20050237839A1
公开(公告)日：2005-10-27
申请号：US11168291
申请日：2005-06-29
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
-
公开(公告)号：US07203116B2
公开(公告)日：2007-04-10
申请号：US11448016
申请日：2006-06-07
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译： 为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时 发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作， 内存操作后。 伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。
-
公开(公告)号：US07082063B2
公开(公告)日：2006-07-25
申请号：US11168291
申请日：2005-06-29
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
-
公开(公告)号：US06928017B2
公开(公告)日：2005-08-09
申请号：US10636558
申请日：2003-08-08
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory in formation from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译： 为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时 发出用于从每个存储单元读取存储器的存储器操作的指令，每个存储器单元需要用于周期性地保持存储器信息的刷新操作或者将其写入其中，执行与之前的存储器操作不同的基于寻址的自主刷新操作 或者在内存操作之后。 伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。
-
公开(公告)号：US06625079B2
公开(公告)日：2003-09-23
申请号：US10175301
申请日：2002-06-20
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the column address signal transition detector.
摘要翻译： 为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时 发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作， 内存操作后。 伪静态RAM包括用于行和列的地址信号转换检测器和根据列地址信号转换检测器的地址信号转换检测信号独立地执行列地址选择操作的页模式。
-
公开(公告)号：US20060227642A1
公开(公告)日：2006-10-12
申请号：US11448016
申请日：2006-06-07
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译： 为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时 发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作， 内存操作后。 伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。
-
公开(公告)号：US07072242B2
公开(公告)日：2006-07-04
申请号：US10965845
申请日：2004-10-18
IPC分类号： G11C8/00
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
-
公开(公告)号：US06377511B1
公开(公告)日：2002-04-23
申请号：US09629173
申请日：2000-07-31
IPC分类号： G11C700
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.025 秒)
