公开(公告)号：US07855416B2

公开(公告)日：2010-12-21

申请号：US12276746

申请日：2008-11-24

申请人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

发明人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

IPC分类号： H01L21/84

CPC分类号： H01L29/78603 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78627

摘要： Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.

摘要翻译： 通道掺杂是用于控制Vth的有效方法，但是当形成诸如在同一衬底上的n沟道TFT和P沟道TFT两者形成的CMOS电路的电路时，Vth偏移到-4至-3V的量级 ，则难以用一个通道掺杂来控制两个TFT的Vth。 为了解决上述问题，本发明在由SiH 4，NH 3和N 2 O制造的氮氧化硅膜（A）和氮氧化硅膜（B）之间的背面通道侧形成阻挡层， 由SiH4和N2O制成。 通过制造这种氮氧化硅膜层压结构，可以防止碱性金属元素从衬底的污染，并且可以减轻施加于TFT的由内部应力引起的应力的影响。

公开(公告)号：US20090224255A1

公开(公告)日：2009-09-10

申请号：US12276746

申请日：2008-11-24

申请人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

发明人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78603 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78627

摘要： Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.

摘要翻译： 通道掺杂是用于控制Vth的有效方法，但是当形成诸如在同一衬底上的n沟道TFT和P沟道TFT两者形成的CMOS电路的电路时，Vth偏移到-4至-3V的量级 ，则难以用一个通道掺杂来控制两个TFT的Vth。 为了解决上述问题，本发明在由SiH 4，NH 3和N 2 O制造的氮氧化硅膜（A）和氮氧化硅膜（B）之间的背面通道侧形成阻挡层， 由SiH4和N2O制成。 通过制造这种氮氧化硅膜层压结构，可以防止碱性金属元素从衬底的污染，并且可以减轻施加于TFT的由内部应力引起的应力的影响。

公开(公告)号：US07456474B2

公开(公告)日：2008-11-25

申请号：US11119431

申请日：2005-04-29

申请人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

发明人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

IPC分类号： H01L27/01

CPC分类号： H01L29/78603 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78627

摘要： Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.

摘要翻译： 通道掺杂是用于控制V th的一种有效的方法，但是当形成诸如CMOS电路之类的电路时，V 3 / 在同一基板上的n沟道TFT和P沟道TFT都是这样，则难以用一个通道掺杂来控制两个TFT的第V个。 为了解决上述问题，本发明在后通道侧形成阻挡层，该阻挡层是由SiH 4 N，NH 3制成的氧氮化硅膜（A） 和N 2 O，以及由SiH 4和N 2 O制成的氮氧化硅膜（B）。 通过制造这种氮氧化硅膜层压结构，可以防止碱性金属元素从衬底的污染，并且可以减轻施加于TFT的由内部应力引起的应力的影响。

公开(公告)号：US20050247934A1

公开(公告)日：2005-11-10

申请号：US11119431

申请日：2005-04-29

申请人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

发明人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

IPC分类号： H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC分类号： H01L29/78603 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78627

摘要： Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.

摘要翻译： 通道掺杂是用于控制V th的一种有效的方法，但是当形成诸如CMOS电路之类的电路时，V 3 / 在同一基板上的n沟道TFT和P沟道TFT都是这样，则难以用一个通道掺杂来控制两个TFT的第V个。 为了解决上述问题，本发明在后通道侧形成阻挡层，该阻挡层是由SiH 4 N，NH 3制成的氧氮化硅膜（A） 和N 2 O，以及由SiH 4和N 2 O制成的氮氧化硅膜（B）。 通过制造这种氮氧化硅膜层压结构，可以防止碱性金属元素从衬底的污染，并且可以减轻施加于TFT的由内部应力引起的应力的影响。

公开(公告)号：US06940124B2

公开(公告)日：2005-09-06

申请号：US10260698

申请日：2002-09-30

申请人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

发明人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

IPC分类号： H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  H01L29/792

CPC分类号： H01L29/78603 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78627

摘要： Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.

公开(公告)号：US06461899B1

公开(公告)日：2002-10-08

申请号：US09558736

申请日：2000-04-26

申请人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

发明人： Hidehito Kitakado ,  Masahiko Hayakawa ,  Shunpei Yamazaki ,  Taketomi Asami

IPC分类号： H01L2184

CPC分类号： H01L29/78603 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78627

摘要： Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of −4 to −3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B)manufactured from SiH4and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.

摘要翻译： 通道掺杂是用于控制Vth的有效方法，但是当形成诸如在同一衬底上的n沟道TFT和P沟道TFT两者形成的CMOS电路的电路时，Vth偏移到-4至-3V的量级 ，则难以用一个通道掺杂来控制两个TFT的Vth。 为了解决上述问题，本发明在由SiH 4，NH 3和N 2 O制造的氮氧化硅膜（A）和氮氧化硅膜（B）之间的背面通道侧形成阻挡层， 由SiH4和N2O制成。 通过制造这种氮氧化硅膜层压结构，可以防止碱性金属元素从衬底的污染，并且可以减轻施加于TFT的由内部应力引起的应力的影响。

公开(公告)号：US07015505B2

公开(公告)日：2006-03-21

申请号：US10684936

申请日：2003-10-14

申请人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/7842 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78636 ,  H01L29/78645 ,  H01L2029/7863

摘要： In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

公开(公告)号：US06380558B1

公开(公告)日：2002-04-30

申请号：US09472137

申请日：1999-12-23

申请人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

IPC分类号： H01L2904

CPC分类号： H01L29/7842 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78636 ,  H01L29/78645 ,  H01L2029/7863

摘要： In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

摘要翻译： 在包括第一绝缘层，结晶半导体层和第二绝缘层的层叠体的半导体器件中，通过从应力平衡的角度来确定其结构，改善了器件的特性。 在包括在基板上具有拉伸应力的结晶半导体层的有源层的半导体器件中，对形成为与基板侧的半导体层的表面紧密接触的第一绝缘层施加拉伸应力，压缩应力 被赋予形成为与衬底侧相反的一侧与半导体层的表面紧密接触的第二绝缘层。

公开(公告)号：US07476577B2

公开(公告)日：2009-01-13

申请号：US11582471

申请日：2006-10-17

申请人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

IPC分类号： H01L21/66 ,  H01L21/00 ,  H01L21/20

CPC分类号： H01L29/7842 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78636 ,  H01L29/78645 ,  H01L2029/7863

摘要： In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

公开(公告)号：US07132686B2

公开(公告)日：2006-11-07

申请号：US11298378

申请日：2005-12-08

申请人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Taketomi Asami ,  Toru Takayama ,  Ritsuko Kawasaki ,  Hiroki Adachi ,  Naoya Sakamoto ,  Masahiko Hayakawa ,  Hiroshi Shibata ,  Yasuyuki Arai

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/7842 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78636 ,  H01L29/78645 ,  H01L2029/7863

摘要： In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.