公开(公告)号：US20120194489A1

公开(公告)日：2012-08-02

申请号：US13501198

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

IPC分类号： G06F3/038 ,  G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

摘要翻译： 构成移位寄存器的各级包括用于增加基于第一时钟（CKA）的扫描信号的电位的输出控制薄膜晶体管，用于增加连接到栅极的第一节点的电位的两个薄膜晶体管 基于从前级/后级输出的扫描信号的输出控制薄膜晶体管的端子和用于降低第一节点的电位的两个薄膜晶体管，基于从 在有关阶段之后的第三阶段。 移位寄存器基于四相时钟信号进行操作，包括提供给奇数级的两相时钟信号和提供给偶数级的两相时钟信号，其中相位偏移90度 彼此。

公开(公告)号：US20130057598A1

公开(公告)日：2013-03-07

申请号：US13698094

申请日：2011-04-18

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

IPC分类号： G09G5/10

CPC分类号： G02F1/136286 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0439

摘要： The present invention provides a display panel having decreased cost and current consumption by decreasing the number of data signal lines from the conventional number, a display device including the display panel, and a method of driving the display device.Each pixel formation portion (10) included in a display unit (200) of a display device is configured to arrange three sub-pixel formation portions (1r, 1g, 1b) for forming sub-pixels of mutually different color components in a data signal line extension direction. Each one data signal line (30) is arranged between a sub-pixel formation portion vertical string (3) in an odd-order from a front of a scanning signal line extension direction and a sub-pixel formation portion vertical string (3) adjacent to the sub-pixel formation portion vertical string (3) at the back of the scanning signal line extension direction. Sub-pixel formation portion vertical strings (3, 3) positioned at both sides of each data signal line (30) are connected to the data signal line. Each one scanning signal line (40) is arranged at both sides of a sub-pixel formation portion in a data signal line extension direction. Mutually adjacent sub-pixel formation portion vertical strings (3, 3) are connected to mutually different scanning signal line (40).

摘要翻译： 本发明提供一种显示面板，其通过从常规数量减少数据信号线的数量，包括显示面板的显示装置和驱动显示装置的方法而具有降低的成本和电流消耗。 包括在显示装置的显示单元（200）中的每个像素形成部分（10）被配置为布置用于在数据信号中形成彼此不同的颜色分量的子像素的三个子像素形成部分（1r，1g，1b） 线延伸方向。 每个数据信号线（30）被布置在从扫描信号线延伸方向的前面开始的奇数级的子像素形成部垂直串（3）和相邻的子像素形成部垂直串（3）之间 到扫描信号线延伸方向后面的子像素形成部分垂直线（3）。 位于每个数据信号线（30）两侧的子像素形成部分垂直弦线（3,3）连接到数据信号线。 每个扫描信号线（40）布置在数据信号线延伸方向上的子像素形成部分的两侧。 相互相邻的子像素形成部垂直串（3,3）连接到相互不同的扫描信号线（40）。

公开(公告)号：US20120200544A1

公开(公告)日：2012-08-09

申请号：US13501215

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

IPC分类号： G06F3/038 ,  G11C19/28

CPC分类号： G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： In a shift register that operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock appears as a potential of a scanning signal, when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

摘要翻译： 在基于四相时钟信号工作的移位寄存器中，包括提供给奇数级的两相时钟信号和提供给偶数级的两相时钟信号，其中相位偏移90 在第一节点的电位处于高电平时，第一时钟的电位在扫描信号的电位下显现。 在这种配置中，基于从前级输出的扫描信号的脉冲将每级中包括的第一节点的电位设置为高电平，并且基于扫描信号的脉冲将其设置为低电平 在有关阶段后从第三阶段输出。

公开(公告)号：US20110134090A1

公开(公告)日：2011-06-09

申请号：US12737649

申请日：2009-05-27

申请人： Akihisa Iwamoto ,  Takayuki Mizunaga ,  Hideki Morii ,  Yuuki Ohta ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Takayuki Mizunaga ,  Hideki Morii ,  Yuuki Ohta ,  Kei Ikuta

IPC分类号： G06F3/038 ,  G11C19/28

CPC分类号： G11C19/184 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

摘要： A control section prepares a control signal and supplies the control signal to a control terminal of a first switching element, the control signal causing the first switching element to turn on in accordance with a non-active voltage level of a storage node and an active voltage level of a second clock signal which active voltage level is obtained in a period in which the second clock signal is active.

摘要翻译： 控制部分准备控制信号，并将控制信号提供给第一开关元件的控制端，该控制信号使得第一开关元件根据存储节点的非有效电压电平和有源电压而导通 在第二时钟信号有效的时段中得到有效电压电平的第二时钟信号的电平。

公开(公告)号：US20120223926A1

公开(公告)日：2012-09-06

申请号：US13504964

申请日：2010-07-07

申请人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Kei Ikuta

发明人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Kei Ikuta

IPC分类号： G09G5/00 ,  G05F1/46

CPC分类号： H02M3/155 ,  G09G3/3696 ,  H02M3/07 ,  H02M2001/009

摘要： An object is to provide at low cost a Power-supply circuit that can generate positive and negative analog power source voltages of which absolute values of voltage values are equal.A Power-supply circuit (210) is configured by a DCDC converter circuit (212) and a charge pump circuit (214). The charge pump circuit (214) includes a diode (D3) that passes a current when a control switch (51) is in an off state, and a diode (D4) that passes a current when the control switch (51) is in an on state. A DCDC converter circuit (212) includes two diodes (D1, D2) that pass a current when the control switch (S1) is in an off state. A rectifying unit that includes the diodes (D1, D2) is configured such that a forward drop voltage of the rectifying unit becomes equal to a sum of a forward drop voltage of the diode (D3) and a forward drop voltage of the diode (D4).

摘要翻译： 目的是提供一种能够产生电压值绝对值相等的正和负模拟电源电压的电源电路。 电源电路（210）由DCDC转换器电路（212）和电荷泵电路（214）构成。 电荷泵电路（214）包括：二极管（D3），当控制开关（51）处于断开状态时，使二极管（D3）通过电流;以及二极管（D4），当控制开关（51）为 在状态。 DCDC转换器电路（212）包括当控制开关（S1）处于断开状态时通过电流的两个二极管（D1，D2）。 包括二极管（D1，D2）的整流单元被配置为使得整流单元的正向压降电压等于二极管（D3）的正向压降电压和二极管（D4）的正向压降电压之和 ）。

公开(公告)号：US08519764B2

公开(公告)日：2013-08-27

申请号：US13501198

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

IPC分类号： H03K3/00

CPC分类号： G11C19/28 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

摘要翻译： 构成移位寄存器的各级包括用于增加基于第一时钟（CKA）的扫描信号的电位的输出控制薄膜晶体管，用于增加连接到栅极的第一节点的电位的两个薄膜晶体管 基于从前级/后级输出的扫描信号的输出控制薄膜晶体管的端子和用于降低第一节点的电位的两个薄膜晶体管，基于从 在有关阶段之后的第三阶段。 移位寄存器基于四相时钟信号进行操作，包括提供给奇数级的两相时钟信号和提供给偶数级的两相时钟信号，其中相位偏移90度 彼此。

公开(公告)号：US20120120044A1

公开(公告)日：2012-05-17

申请号：US13380375

申请日：2010-01-27

申请人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Yuuki Ohta ,  Kei Ikuta

发明人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Yuuki Ohta ,  Kei Ikuta

IPC分类号： G09G5/00

CPC分类号： G09G3/3614 ,  G09G3/3655 ,  G09G2310/0205 ,  G09G2310/0251 ,  G09G2310/0283 ,  G09G2310/067 ,  G09G2320/0247 ,  G09G2320/046

摘要： Provided is a liquid crystal display device performing a precharge and having a function of switching an order for selecting scanning lines, in which such as flicker and burn-in can be prevented from being produced. A scanning line drive circuit selects scanning lines either in ascending order or in descending order based on an order of arrangement according to a shift direction signal, and causes selection periods of the scanning lines to be partially overlapped for a precharge. A data line drive circuit applies voltages of different polarities to data lines by frame and by data line. A common voltage generating circuit generates two types of voltages whose levels are independently adjustable, selects one of the two voltages according to a scan selection signal and applies the selected voltage to a common electrode of a liquid crystal panel. As the common voltage generating circuit, a D/A converter may be used.

摘要翻译： 提供一种执行预充电并具有切换用于选择扫描线的顺序的功能的液晶显示装置，其中可以防止诸如闪烁和老化的产生。 扫描线驱动电路基于根据移位方向信号的布置顺序以升序或降序选择扫描线，并且使扫描线的选择周期部分地重叠用于预充电。 数据线驱动电路按数据线和数据线对数据线施加不同极性的电压。 公共电压产生电路产生电平独立可调的两种电压，根据扫描选择信号选择两个电压中的一个，并将所选择的电压施加到液晶面板的公共电极。 作为公共电压发生电路，可以使用D / A转换器。

公开(公告)号：US20110234565A1

公开(公告)日：2011-09-29

申请号：US12998766

申请日：2009-08-07

申请人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Kei Ikuta

发明人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Kei Ikuta

IPC分类号： G06F3/038 ,  G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/0286

摘要： In at least one embodiment, under a non-load condition of a first supply line for a first clock signal and a second supply line for a second clock signal, a fall time of a clock pulse of the first clock signal, which is supplied to the first supply line, is longer than that of the second clock signal, which is supplied to the second supply line.

摘要翻译： 在至少一个实施例中，在用于第一时钟信号的第一电源线和第二时钟信号的第二电源线的非负载条件下，将第一时钟信号的时钟脉冲的下降时间提供给 第一电源线比第二电源线的第二时钟信号长。

公开(公告)号：US08531224B2

公开(公告)日：2013-09-10

申请号：US13501215

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

IPC分类号： H03K3/00

CPC分类号： G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver.In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

摘要翻译： 目的是在单片门驱动器内的移位寄存器中抑制时钟下降周期，同时抑制电路面积的增加，电流消耗的增加和成本增加，而不产生异常操作。 在基于提供给奇数级的两相时钟信号（GCK1，GCK3）和提供给奇数级的两相时钟信号（GCK2，GCK4）的四相时钟信号的移位寄存器（410）中， 到相位相互偏移90度的偶数级，当第一节点的电位处于高电平时，第一时钟（CKA）的电位作为扫描信号（GOUT）的电位出现 水平，在每个阶段。 在这种配置中，基于从前级输出的扫描信号的脉冲将每级中包括的第一节点的电位设置为高电平，并且基于扫描信号的脉冲将其设置为低电平 在有关阶段后从第三阶段输出。

公开(公告)号：US20100325466A1

公开(公告)日：2010-12-23

申请号：US12735708

申请日：2008-12-04

申请人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Masahiro Hirokane

发明人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Masahiro Hirokane

IPC分类号： G06F1/04 ,  G06F1/12 ,  G02F1/1333

CPC分类号： G09G3/3677 ,  G11C19/28

摘要： In at least one embodiment, a display panel drive circuit including a shift register including unit circuits connected in cascade, each of the unit circuits outputting a signal line selection signal, is configured such that: each of the unit circuits receives a clock signal and either a signal line selection signal outputted from another-stage unit circuit or a start pulse signal; and the clock signal has a rising portion which is caused by activation of the clock signal and which is sloped or a falling portion which is caused by activation of the clock signal and which is sloped. With the configuration, it is possible to realize a display panel drive circuit and a display panel driving method each of which hardly causes a poor gate-on pulse signal (which causes unevenness in electric potential during inactivation, for example.

摘要翻译： 在至少一个实施例中，包括移位寄存器的显示面板驱动电路，其包括级联连接的单元电路，输出信号线选择信号的每个单位电路被配置为：每个单元电路接收时钟信号， 从另一级单元电路输出的信号线选择信号或起始脉冲信号; 并且时钟信号具有由时钟信号的激活引起的上升部分，并且是由于时钟信号的激活而导致的倾斜的下降部分和倾斜的。 通过这样的结构，能够实现显示面板驱动电路和显示面板驱动方法，每个显示面板驱动电路和显示面板驱动方法几乎不会导致差的导通脉冲信号（例如在失活期间导致电位不均匀）。