公开(公告)号：US5131072A

公开(公告)日：1992-07-14

申请号：US474055

申请日：1990-04-30

申请人： Hideki Yoshizawa ,  Hiroki Iciki ,  Hideki Kato ,  Yoshihide Sugiura ,  Kazuo Asakawa ,  Hiroyuki Tsuzuki ,  Hideichi Endo ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Chikara Tsuchiya ,  Katsuya Ishikawa ,  Hiromu Iwamoto

发明人： Hideki Yoshizawa ,  Hiroki Iciki ,  Hideki Kato ,  Yoshihide Sugiura ,  Kazuo Asakawa ,  Hiroyuki Tsuzuki ,  Hideichi Endo ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Chikara Tsuchiya ,  Katsuya Ishikawa ,  Hiromu Iwamoto

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/0635

摘要： An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation. Accordingly, the prsent invention can provide a neuron computer with a high practicality.

公开(公告)号：US5220559A

公开(公告)日：1993-06-15

申请号：US400826

申请日：1989-08-30

申请人： Hiroyuki Tsuzuki ,  Hideichi Endo ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Kazuo Asakawa ,  Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Hiromu Iwamoto ,  Chikara Tsuchiya ,  Katsuya Ishikawa ,  Yoshihide Sugiura

发明人： Hiroyuki Tsuzuki ,  Hideichi Endo ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Kazuo Asakawa ,  Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Hiromu Iwamoto ,  Chikara Tsuchiya ,  Katsuya Ishikawa ,  Yoshihide Sugiura

IPC分类号： G06N3/04

CPC分类号： G06N3/04

摘要： An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.