公开(公告)号：US5131072A

公开(公告)日：1992-07-14

申请号：US474055

申请日：1990-04-30

申请人： Hideki Yoshizawa ,  Hiroki Iciki ,  Hideki Kato ,  Yoshihide Sugiura ,  Kazuo Asakawa ,  Hiroyuki Tsuzuki ,  Hideichi Endo ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Chikara Tsuchiya ,  Katsuya Ishikawa ,  Hiromu Iwamoto

发明人： Hideki Yoshizawa ,  Hiroki Iciki ,  Hideki Kato ,  Yoshihide Sugiura ,  Kazuo Asakawa ,  Hiroyuki Tsuzuki ,  Hideichi Endo ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Chikara Tsuchiya ,  Katsuya Ishikawa ,  Hiromu Iwamoto

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/0635

摘要： An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation. Accordingly, the prsent invention can provide a neuron computer with a high practicality.

公开(公告)号：US5220559A

公开(公告)日：1993-06-15

申请号：US400826

申请日：1989-08-30

申请人： Hiroyuki Tsuzuki ,  Hideichi Endo ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Kazuo Asakawa ,  Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Hiromu Iwamoto ,  Chikara Tsuchiya ,  Katsuya Ishikawa ,  Yoshihide Sugiura

发明人： Hiroyuki Tsuzuki ,  Hideichi Endo ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Kazuo Asakawa ,  Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Hiromu Iwamoto ,  Chikara Tsuchiya ,  Katsuya Ishikawa ,  Yoshihide Sugiura

IPC分类号： G06N3/04

CPC分类号： G06N3/04

摘要： An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.

公开(公告)号：US5216746A

公开(公告)日：1993-06-01

申请号：US486647

申请日：1990-02-28

申请人： Hideki Yoshizawa ,  Hiroki Iciki ,  Hideki Kato ,  Kazuo Asakawa ,  Yoshihide Sugiura ,  Hiroyuki Tsuzuki ,  Hideichi Endoh ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Hiromu Iwamoto ,  Chikara Tsuchiya ,  Katsuya Ishikawa

发明人： Hideki Yoshizawa ,  Hiroki Iciki ,  Hideki Kato ,  Kazuo Asakawa ,  Yoshihide Sugiura ,  Hiroyuki Tsuzuki ,  Hideichi Endoh ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Hiromu Iwamoto ,  Chikara Tsuchiya ,  Katsuya Ishikawa

IPC分类号： G06N3/04

CPC分类号： G06N3/04

摘要： An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors. The weight correcting unit calculates a correct weight using a gain based on the detection output voltage output from the second analog bus. A weight memory stores the weight corrected by the weight correcting unit.

公开(公告)号：US5142666A

公开(公告)日：1992-08-25

申请号：US486644

申请日：1990-02-28

申请人： Hideki Yoshizawa ,  Hiroki Iciki ,  Hideki Kato ,  Kazuo Asakawa ,  Yoshihide Sugiura ,  Hiroyuki Tsuzuki ,  Hideichi Endoh ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Hiromu Iwamoto ,  Chikara Tsuchiya ,  Katsuya Ishikawa

发明人： Hideki Yoshizawa ,  Hiroki Iciki ,  Hideki Kato ,  Kazuo Asakawa ,  Yoshihide Sugiura ,  Hiroyuki Tsuzuki ,  Hideichi Endoh ,  Takashi Kawasaki ,  Toshiharu Matsuda ,  Hiromu Iwamoto ,  Chikara Tsuchiya ,  Katsuya Ishikawa

IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/02 ,  G06N3/04 ,  G06N3/08 ,  G06N99/00

CPC分类号： G06N3/04

摘要： A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.

公开(公告)号：US5600843A

公开(公告)日：1997-02-04

申请号：US227472

申请日：1994-04-14

申请人： Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Kazuo Asakawa

发明人： Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Kazuo Asakawa

IPC分类号： G06F15/173 ,  G06F15/80 ,  G06N3/10 ,  G06F15/16

CPC分类号： G06N3/10 ,  G06F15/17337 ,  G06F15/8015

摘要： A parallel data processing system comprises a plurality of data processing units each having at least one input and storing data of a matrix and a plurality of trays each having a first input and an output and for storing data of a vector, each of all or part of said trays having a second output connected to said first input of a respective one of said data processing units, and said trays being connected in cascade to form a shift register for performing data transfer between corresponding ones of the trays and the data processing units and data processing in the data processing units synchronously, thereby performing an operation of a matrix vector product or a neuron computer operation on analog signals.

摘要翻译： 并行数据处理系统包括多个数据处理单元，每个数据处理单元具有至少一个输入和存储矩阵的数据和多个托盘，每个托盘具有第一输入和输出，并且用于存储向量的数据，全部或部分 所述托盘具有连接到所述数据处理单元的相应一个的所述第一输入的第二输出，并且所述托盘级联连接以形成移位寄存器，用于在相应的托盘和数据处理单元之间执行数据传输， 数据处理单元中的数据处理同步，从而对模拟信号进行矩阵向量积或神经元计算机操作。

公开(公告)号：US5506998A

公开(公告)日：1996-04-09

申请号：US261889

申请日：1994-06-17

申请人： Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Daiki Masumoto

发明人： Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Daiki Masumoto

IPC分类号： G06F15/18 ,  G06F15/80 ,  G06F17/16 ,  G06N3/02 ,  G06N3/10 ,  G06N99/00 ,  G06F13/00 ,  G06F15/16 ,  G06F15/31

CPC分类号： G06N3/10 ,  G06F15/8015

摘要： A parallel data processing system performs a data processing by using a plurality of data processing units, namely, processor elements, synchronously. The parallel data processing system comprises a plurality of data processing units, a plurality of trays, and a clock generator. The plurality of trays are connected to respective data processing units and have a function of storing a plurality of data and a function of transmitting the data. The clock generator is producing a clock so that the data transfer between the trays and between the trays and the data processing units, and the data processing in the data processing unit is executed synchronously. Data are transferred between trays during the period in which they are processed, thus substantially eliminating the data transmission time. Furthermore, the interim result of the operation is stored in the tray and thus when the later operation needs the interim result, the interim result stored in the tray is efficiently used without the need to access the memory provided in the data processing apparatus.

摘要翻译： 并行数据处理系统通过使用多个数据处理单元即处理器元件同步地执行数据处理。 并行数据处理系统包括多个数据处理单元，多个托盘和时钟发生器。 多个托盘连接到相应的数据处理单元，并且具有存储多个数据的功能和发送数据的功能。 时钟发生器正在产生时钟，使得盘之间以及盘与数据处理单元之间的数据传输以及数据处理单元中的数据处理被同步地执行。 在处理它们的时间段期间，在托盘之间传送数据，从而基本上消除了数据传输时间。 此外，操作的中期结果存储在托盘中，因此当稍后的操作需要临时结果时，有效地使用存储在托盘中的中期结果，而不需要访问数据处理设备中提供的存储器。

公开(公告)号：US5544336A

公开(公告)日：1996-08-06

申请号：US420332

申请日：1995-04-11

申请人： Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Daiki Masumoto

发明人： Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki ,  Daiki Masumoto

IPC分类号： G06F15/16 ,  G06F15/177 ,  G06N3/10 ,  G06F3/00

CPC分类号： G06N3/10

摘要： A parallel data processing system processes data by synchronously operating a plurality of data processing units (processor elements). It aims at reducing the overhead caused by the data transmission in a system, performing a matrix operation and a neurocomputer operation by making the best of its parallel processing method, and at using excess units for another operation when the number of units required for an operation is smaller than the number of the existing units. The parallel data processing system comprises a plurality of data processing units; a plurality of trays which store and transmit data, each connected to a data processing unit; a tray connection switching unit for changing the connection state of the data transmission path between trays, dividing data processing units into a plurality of groups, and performing an independent operation on each group; and a clock generator for synchronously operating a data transmission between trays and a data process in a data processing unit. Thus, the data are transmitted while the data are processed, so the data transmission time can be actually counted as zero.

摘要翻译： 并行数据处理系统通过同步操作多个数据处理单元（处理器元件）来处理数据。 其目的在于减少系统中的数据传输引起的开销，通过充分利用其并行处理方法执行矩阵运算和神经计算机操作，并且在运行所需的单元数量的情况下使用多余的单位进行另一操作 小于现有单位的数量。 并行数据处理系统包括多个数据处理单元; 存储和发送数据的多个托盘，每个托盘连接到数据处理单元; 托盘连接切换单元，用于改变托盘之间的数据传输路径的连接状态，将数据处理单元划分成多个组，并对每个组执行独立操作; 以及时钟发生器，用于同步地操作数据处理单元中的托盘与数据处理之间的数据传输。 因此，在处理数据的同时发送数据，因此数据传输时间实际上可以被计数为零。

公开(公告)号：US5220660A

公开(公告)日：1993-06-15

申请号：US722198

申请日：1991-06-27

申请人： Hideki Yoshizawa ,  Hideki Kato ,  Hiroki Iciki ,  Daiki Masumoto

发明人： Hideki Yoshizawa ,  Hideki Kato ,  Hiroki Iciki ,  Daiki Masumoto

IPC分类号： G06F15/16 ,  G06F1/10 ,  G06F9/52 ,  G06F15/177 ,  G06F15/80

CPC分类号： G06F1/10

摘要： A parallel data processing apparatus including a plurality of processors, a pair of signal paths are provided for each processor, one signal path of each pair being used for supplying a predetermined signal to the processor, and the second signal path being used for returning the signal from the processor to a predetermined position common to all of the processors. Each of the above signal paths include a variable delay unit. The apparatus further includes a delay measuring unit for measuring the time elapsing while the signal is propagated from the above predetermined position to a corresponding processor and then returned from the processor to the above predetermined position through each pair of signal paths. Further the apparatus includes a delay adjusting unit for adjusting the delays caused by the variable delay units in all of the signal paths. The delay adjustment are based on the results of a measurement by the delay measuring unit, so that the time elapsing while the signal is propagated from the predetermined position to the plurality of processors, through the respective signal paths for supplying the signal to the processors, are equal.

公开(公告)号：US5369731A

公开(公告)日：1994-11-29

申请号：US757344

申请日：1991-09-10

申请人： Daiki Masumoto ,  Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki

发明人： Daiki Masumoto ,  Hideki Kato ,  Hideki Yoshizawa ,  Hiroki Iciki

IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/02 ,  G06N3/04 ,  G06N99/00

CPC分类号： G06N3/04

摘要： An asynchronous control system for a neuro computer, includes an inter-connected type neural network composed of a plurality of neurons for multiplying a plurality of input signals with corresponding weights, calculating a total sum-of-products of the input signals and weight, thereby providing the sum-of product signals, and converting the sum-of-product signal using a non-linear function. A weight memory is provided for storing data of the weights for said neurons, and a controller is provided for generating a control pattern which controls the neural network. A selector randomly selects one of the neurons which performs signal processing during one processing cycle.

摘要翻译： 用于神经计算机的异步控制系统包括由多个神经元组成的互连型神经网络，用于将多个输入信号与相应权重相乘，计算输入信号和权重的总和积，由此 提供乘积信号之和，并使用非线性函数来转换积和积信号。 提供权重存储器用于存储所述神经元的权重的数据，并且提供控制器用于产生控制神经网络的控制模式。 选择器在一个处理周期内随机选择执行信号处理的一个神经元。

公开(公告)号：US08281113B2

公开(公告)日：2012-10-02

申请号：US12618954

申请日：2009-11-16

申请人： Hideki Yoshizawa

发明人： Hideki Yoshizawa

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30014 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3875

摘要： An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a plurality of pipeline registers provided so as to separate the pipeline stages from each other, wherein each of the pipeline registers operates in such a manner as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output.

摘要翻译： 用于在处理器的执行阶段中执行规定位长的操作的算术逻辑单元包括多个子算术逻辑单元，它们分别在不同的流水线级执行通过分解规定位的操作而产生的子操作 以及多个流水线寄存器，其被设置为将流水线级彼此分离，其中每个流水线寄存器以可在两种操作模式之间切换的方式操作，触发器模式 其中输出值与输入触发和输入值直接输出的透明模式同步更新。