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公开(公告)号：US5131072A
公开(公告)日：1992-07-14
申请号：US474055
申请日：1990-04-30
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
CPC分类号： G06N3/063 , G06N3/04 , G06N3/0635
摘要： An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation. Accordingly, the prsent invention can provide a neuron computer with a high practicality.
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公开(公告)号：US5220559A
公开(公告)日：1993-06-15
申请号：US400826
申请日：1989-08-30
申请人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
发明人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.
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公开(公告)号：US5216746A
公开(公告)日：1993-06-01
申请号：US486647
申请日：1990-02-28
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors. The weight correcting unit calculates a correct weight using a gain based on the detection output voltage output from the second analog bus. A weight memory stores the weight corrected by the weight correcting unit.
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公开(公告)号：US5142666A
公开(公告)日：1992-08-25
申请号：US486644
申请日：1990-02-28
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
CPC分类号： G06N3/04
摘要： A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.
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公开(公告)号：US20120105900A1
公开(公告)日：2012-05-03
申请号：US13282544
申请日：2011-10-27
申请人： Hiroyuki Tsuzuki , Kimitoshi Sato
发明人： Hiroyuki Tsuzuki , Kimitoshi Sato
IPC分类号： G06K15/02
CPC分类号： G06K15/4095 , G06F21/608
摘要： An image forming apparatus performs a direct printing function. A selecting section selects at least two files from a plurality of files stored in at least one of an internal storage medium and an external storage medium. A human interface receives passwords form a user. A password determining section determines whether the selected files are protected by passwords. A file extracting section extracts the selected files from an internal storage medium or external storage medium. A password verifying section determines whether passwords contained in the selected files and the passwords inputted through the human interface coincide. A printer prints the selected files. A printing controller controls the printer, causing the printer to print at least one of selected files if the password verifying section has determined that the password contained in the at least one selected file and the password inputted by the user coincide.
摘要翻译： 图像形成装置执行直接打印功能。 选择部分从存储在内部存储介质和外部存储介质中的至少一个中的多个文件中选择至少两个文件。 人机接口从用户那里接收密码。 密码确定部分确定所选文件是否受密码保护。 文件提取部从内部存储介质或外部存储介质中提取所选择的文件。 密码验证部分确定所选文件中包含的密码和通过人机界面输入的密码是否一致。 打印机打印所选文件。 打印控制器控制打印机，如果密码验证部分已确定包含在至少一个所选文件中的密码和用户输入的密码一致，则打印机至少打印一个所选文件。
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公开(公告)号：USD519996S1
公开(公告)日：2006-05-02
申请号：US29223149
申请日：2005-02-10
申请人： Hiroyuki Tsuzuki , Tadao Hosaka , Tetsuya Nagata
设计人： Hiroyuki Tsuzuki , Tadao Hosaka , Tetsuya Nagata
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7.发明授权公开(公告)号：US06626692B2
公开(公告)日：2003-09-30
申请号：US10054478
申请日：2002-01-22
申请人： Toshihiko Maeda , Yoshinori Mizusawa , Osamu Hashiguchi , Kazuomi Sato , Hisashi Ishida , Hiroyuki Tsuzuki , Masahiro Yamada , Masahiro Yamauchi
发明人： Toshihiko Maeda , Yoshinori Mizusawa , Osamu Hashiguchi , Kazuomi Sato , Hisashi Ishida , Hiroyuki Tsuzuki , Masahiro Yamada , Masahiro Yamauchi
IPC分类号： H01R13627
CPC分类号： H01R13/518 , B63B22/04 , F16B5/02 , H01R13/6272 , H01R13/62905 , H01R13/64 , H04Q1/023 , H04Q1/14 , Y10S439/953 , Y10S439/954
摘要： There is provided an insertion and withdrawal connector apparatus in which a plurality of connectors can move only in a range of capable of engaging and separating with and from a plurality of mating connectors within a connector receiving body. A connector receiving body (1) has a pair of parallel frames (3), a pair of frame blocks (4) positioned at both end portions, and a plurality of partition members (5). One connector (10) and one mating connector are received in each of a plurality of space portions, that is, receiving chambers partitioned by a pair of frames, a pair of frame blocks, and a plurality of partition members. Each of the partition members has a pair of lances (5f, 5g) having a spring characteristic and each of the connectors has a pair of interlocking groove portions (10g) on both side surfaces. The lance (5f) interlocks with the interlocking groove portion on one of the side surfaces in the connector, and the lance (5g) interlocks with the interlocking groove portion on the other of the side surfaces in the connector. Each of the connectors has a convex portion (10d) at an upper end portion on one of the side surfaces and at a lower end portion on the other of the side surfaces, and each of the convex portions interlocks with each of the partition members.
摘要翻译： 提供了插入和取出连接器装置，其中多个连接器只能在能够与连接器接收体内的多个配合连接器接合和分离的范围内移动。 连接器接收体（1）具有一对平行框架（3），位于两端部的一对框架块（4）和多个分隔构件（5）。 一个连接器（10）和一个配合连接器被接收在多个空间部分中的每一个中，即，由一对框架分隔的接收室，一对框架块和多个分隔构件。 每个分隔构件具有一对具有弹簧特性的喷枪（5f，5g），并且每个连接器在两个侧表面上具有一对互锁槽部分（10g）。 喷枪（5f）与连接器中的一个侧表面上的互锁槽部互锁，并且喷枪（5g）与连接器中的另一侧面上的互锁槽部互锁。 每个连接器在一个侧表面上的上端部和另一个侧表面的下端部处具有凸部（10d），并且每个凸部与每个分隔构件互锁。
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公开(公告)号：US06149447A
公开(公告)日：2000-11-21
申请号：US145844
申请日：1998-09-02
申请人： Toshihiko Maeda , Yoshinori Mizusawa , Osamu Hashiguchi , Kazuomi Sato , Hisashi Ishida , Hiroyuki Tsuzuki , Masahiro Yamada , Masahiro Yamauchi
发明人： Toshihiko Maeda , Yoshinori Mizusawa , Osamu Hashiguchi , Kazuomi Sato , Hisashi Ishida , Hiroyuki Tsuzuki , Masahiro Yamada , Masahiro Yamauchi
IPC分类号： B63B22/04 , H01R13/518 , H01R13/629 , H04Q1/14 , H01R13/62
CPC分类号： H01R13/518 , B63B22/04 , F16B5/02 , H01R13/62905 , H01R13/64 , H04Q1/023 , H04Q1/14 , H01R13/6272 , Y10S439/953 , Y10S439/954
摘要： There is provided an insertion and withdrawal connector apparatus in which a plurality of connectors can move only in a range of capable of engaging and separating with and from a plurality of mating connectors within a connector receiving body. A connector receiving body (1) has a pair of parallel frames (3), a pair of frame blocks (4) positioned at both end portions, and a plurality of partition members (5). One connector (10) and one mating connector are received in each of a plurality of space portions, that is, receiving chambers partitioned by a pair of frames, a pair of frame blocks, and a plurality of partition members. Each of the partition members has a pair of lances (5f, 5g) having a spring characteristic and each of the connectors has a pair of interlocking groove portions (10g) on both side surfaces. The lance (5f) interlocks with the interlocking groove portion on one of the side surfaces in the connector, and the lance (5g) interlocks with the interlocking groove portion on the other of the side surfaces in the connector. Each of the connectors has a convex portion (10d) at an upper end portion on one of the side surfaces and at a lower end portion on the other of the side surfaces, and each of the convex portions interlocks with each of the partition members.
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公开(公告)号：USD429721S
公开(公告)日：2000-08-22
申请号：US97220
申请日：1998-12-02
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公开(公告)号：USD419536S
公开(公告)日：2000-01-25
申请号：US98542
申请日：1998-12-30
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