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38 条记录 (耗时 0.042 秒)

    Detection circuit for amplitude modulated signals
    5.
    发明授权
    Detection circuit for amplitude modulated signals 失效
    用于振幅调制信号的检测电路

    公开(公告)号：US5126683A

    公开(公告)日：1992-06-30

    申请号：US587685

    申请日：1990-09-25

    申请人： Katsuya Ishikawa ,  Yasuhiro Hashimoto ,  Chikara Tsuchiya

    发明人： Katsuya Ishikawa ,  Yasuhiro Hashimoto ,  Chikara Tsuchiya

    IPC分类号： H03D1/18

    CPC分类号： H03D1/18

    摘要： A detection circuit of amplitude modulated signals comprises a first bipolar transistor having a base connected to an input terminal, a collector connected to a first voltage source providing a first power voltage and an emitter; a second bipolar transistor having a base, a collector connected to the first voltage source, and an emitter which is coupled commonly to the emitter of the first bipolar transistor; an output terminal connected commonly to the emitter of the first bipolar transistor and the emitter of the second bipolar transistor for providing an output signal; a biasing circuit connected to the base of the first bipolar transistor and to the base of the second bipolar transistor for biasing the first and second bipolar transistor; a control circuit having an input terminal connected to the base of the first bipolar transistor for producing a control signal in response to an amplitude modulated signal supplied to the input terminal; and a variable current source having a first end connected to the emitters of the first and second bipolar transistors, and a second end connected to a second voltage source providing a second power voltage which is different from the first power voltage, for causing to flow therethrough a drive current to the second voltage source, wherein the control circuit contols the variable current source by the control signal such that the output signal at the output terminal has a voltage level which increases linearly with increasing amplitude of the input amplitude modulated signal in one of positive and negative half cycles of the amplitude modulated signal and such that the output signal has a constant voltage level in the other of the positive and negative half cycles of the amplitude modulated signal.

    Ring oscillator having outputs that are selectively combined to produce different frequencies
    6.
    发明授权
    Ring oscillator having outputs that are selectively combined to produce different frequencies 失效
    具有选择性地组合以产生不同频率的输出的环形振荡器

    公开(公告)号：US5262735A

    公开(公告)日：1993-11-16

    申请号：US915251

    申请日：1992-07-20

    申请人： Yasuhiro Hashimoto ,  Katsuya Ishikawa ,  Chikara Tsuchiya

    发明人： Yasuhiro Hashimoto ,  Katsuya Ishikawa ,  Chikara Tsuchiya

    IPC分类号： H03F3/68 ,  H03F3/45 ,  H03K3/0231 ,  H03K3/03 ,  H03K3/282 ,  H03K19/018 ,  H03B5/02 ,  H03B27/00

    CPC分类号： H03K3/0231

    摘要： A ring oscillator comprises a plurality of amplifiers connected in a multi-stage connection and each including a pair of output terminals from which first output signals are issued respectively; a pair of input terminals to which another pair of output terminals of a last stage amplifier are connected, respectively, and an amplifying circuit arranged between the output terminals and the input terminals. An oscillating signal can be generated by taking out the respectively corresponding second output signals from the amplifiers and combining these second output signals. The ring oscillator is constructed such that the second output signals are taken out from any middle output terminals in the amplifying circuit, other than the output terminals and the input terminals. Preferably, the amplifying circuit includes differential amplifying units each having a pair of differential transistors and a pair of emitter follower units having emitter follower transistors, respectively, and the second output signals are taken out from any portions among the output portions of the emitter follower units and all stage amplifying units other than the final stage differential amplifying unit.

    摘要翻译： 环形振荡器包括以多级连接方式连接的多个放大器，每个放大器包括分别发出第一输出信号的一对输出端子; 分别连接最后一级放大器的另一对输出端子的一对输入端子和布置在输出端子和输入端子之间的放大电路。 可以通过从放大器中取出分别对应的第二输出信号并组合这些第二输出信号来产生振荡信号。 环形振荡器被构造成使得除了输出端子和输入端子之外，第二输出信号从放大电路中的任何中间输出端子被取出。 优选地，放大电路包括分别具有一对差分晶体管和一对具有射极跟随器晶体管的射极跟随器单元的差分放大单元，并且第二输出信号从射极跟随器单元的输出部分中的任何部分中取出 以及除了末级差分放大单元以外的所有级放大单元。

    Active rectifying apparatus
    7.
    发明授权
    Active rectifying apparatus 有权
    主动整流装置

    公开(公告)号：US08416015B2

    公开(公告)日：2013-04-09

    申请号：US13078386

    申请日：2011-04-01

    申请人： Chikara Tsuchiya

    发明人： Chikara Tsuchiya

    IPC分类号： H03K17/74 ,  H03G11/02

    CPC分类号： H03K17/302 ,  H01L27/0817 ,  H01L27/088 ,  H03K2017/307

    摘要： A semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a gate voltage of the first transistor.

    摘要翻译： 一种半导体装置，包括：第一晶体管; 第二晶体管具有比第一晶体管更高的耐受电压，第二晶体管的源极耦合到第一晶体管的漏极，第二晶体管的栅极耦合到第一晶体管的源极; 具有比第一晶体管更高的耐受电压的第三晶体管和耦合到第二晶体管的漏极的第三晶体管的漏极; 以及比较器，其将第一晶体管的源极电压与第三晶体管的源极电压进行比较，并且控制第一晶体管的栅极电压。

    DC/DC converter
    8.
    发明授权
    DC/DC converter 有权
    DC / DC转换器

    公开(公告)号：US07019501B2

    公开(公告)日：2006-03-28

    申请号：US10806150

    申请日：2004-03-23

    申请人： Hirofumi Dogome ,  Takashi Matsumoto ,  Kyuichi Takimoto ,  Hidekiyo Ozawa ,  Chikara Tsuchiya

    发明人： Hirofumi Dogome ,  Takashi Matsumoto ,  Kyuichi Takimoto ,  Hidekiyo Ozawa ,  Chikara Tsuchiya

    IPC分类号： G05F1/40

    CPC分类号： H02M3/158 ,  H02J7/0065 ,  H02M1/088

    摘要： A DC/DC converter enabling an increase in frequency. The DC/DC converter includes a main transistor, a synchronization transistor, a control circuit, which controls the main transistor and the synchronization transistor, and a capacitor, which is charged to generate gate voltage for the main transistor. The control circuit includes a charging time setting circuit for setting the activation time of the main transistor and the synchronization transistor.

    摘要翻译： DC / DC转换器，能够提高频率。 DC / DC转换器包括主晶体管，同步晶体管，控制主晶体管和同步晶体管的控制电路以及被充电以产生主晶体管的栅极电压的电容器。 控制电路包括用于设定主晶体管和同步晶体管的激活时间的充电时间设定电路。

    A/D converter with reduced power consumption
    9.
    发明授权
    A/D converter with reduced power consumption 失效
    A / D转换器，功耗降低

    公开(公告)号：US06888488B2

    公开(公告)日：2005-05-03

    申请号：US10304756

    申请日：2002-11-27

    申请人： Hiroshi Takakusagi ,  Toshitaka Mizuguchi ,  Chikara Tsuchiya ,  Katsuyosi Yamamoto

    发明人： Hiroshi Takakusagi ,  Toshitaka Mizuguchi ,  Chikara Tsuchiya ,  Katsuyosi Yamamoto

    IPC分类号： H03M1/36 ,  H03K5/08 ,  H03K5/24 ,  H03M1/00

    CPC分类号： H03K5/249 ,  H03M1/002 ,  H03M1/36

    摘要： An A/D converter includes a plurality of comparators, each of which samples an analog input potential during a first period, and compares the analog input potential with a reference potential during a second period, an encoder which encodes comparison results obtained by the comparators, and a control signal supply unit which generates one or more control signals that define the first period and the second period such as to make a duration of the first period different from a duration of the send period, and supplies the one or more control signals to the plurality of comparators.

    摘要翻译： A / D转换器包括多个比较器，每个比较器在第一周期期间采样模拟输入电位，并且在第二周期期间将模拟输入电位与参考电位进行比较，编码器编码由比较器获得的比较结果， 以及控制信号提供单元，其产生定义第一周期和第二周期的一个或多个控制信号，以使得第一周期的持续时间不同于发送周期的持续时间，并将一个或多个控制信号提供给 多个比较器。