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1.发明授权Semiconductor integrated circuit device having logic circuit and dynamic random access memory on the same chip 有权具有在同一芯片上的逻辑电路和动态随机存取存储器的半导体集成电路器件公开(公告)号：US07102954B2
公开(公告)日：2006-09-05
申请号：US10714393
申请日：2003-11-17
CPC分类号： H01L27/10897 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C29/12
摘要： In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.
摘要翻译： 在存储器电路中，以与逻辑晶体管相同的工艺形成的晶体管用于外围电路，除了要被提供高电压的区域之外。 因此，可以简化制造过程，并且提供以高速运行的逻辑合并存储器。
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公开(公告)号：US06649984B1
公开(公告)日：2003-11-18
申请号：US09632333
申请日：2000-08-03
IPC分类号： H01L29792
CPC分类号： H01L27/10897 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C29/12
摘要： In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.
摘要翻译： 在存储器电路中，以与逻辑晶体管相同的工艺形成的晶体管用于外围电路，除了要被提供高电压的区域之外。 因此，可以简化制造过程，并且提供以高速运行的逻辑合并存储器。
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公开(公告)号：US20090070525A1
公开(公告)日：2009-03-12
申请号：US12268017
申请日：2008-11-10
IPC分类号： G06F12/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门 用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。 匹配线用作水平位线对或用于访问水平端口的信号线。 当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。 此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。
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公开(公告)号：US08089819B2
公开(公告)日：2012-01-03
申请号：US12857063
申请日：2010-08-16
IPC分类号： G11C7/06
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译： 存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。 在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。 在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。 以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。
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公开(公告)号：US20070058407A1
公开(公告)日：2007-03-15
申请号：US11517441
申请日：2006-09-08
IPC分类号： G11C15/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门 用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。 匹配线用作水平位线对或用于访问水平端口的信号线。 当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。 此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。
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公开(公告)号：US20060143428A1
公开(公告)日：2006-06-29
申请号：US11282714
申请日：2005-11-21
CPC分类号： G06F7/785 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C8/16 , G11C11/419 , G11C2207/104
摘要： An orthogonal memory for transforming arrangements of system bus data and processing data is placed between a system bus interface and a memory cell mat storing the processing data. The orthogonal memory includes two-port memory cells, and changes data train transferred in a bit parallel and word serial fashion into a data train of word parallel and bit serial data. Data transfer efficiency in a signal processing device performing parallel operational processing can be increased without impairing parallelism of the processing.
摘要翻译： 用于变换系统总线数据和处理数据的布置的正交存储器被放置在系统总线接口和存储处理数据的存储单元矩阵之间。 正交存储器包括双端口存储器单元，并且将以位并行和字串行方式传送的数据串改变成字并行和位串行数据的数据串。 可以增加执行并行操作处理的信号处理装置中的数据传送效率，而不会削弱处理的并行性。
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公开(公告)号：US08077492B2
公开(公告)日：2011-12-13
申请号：US12268017
申请日：2008-11-10
IPC分类号： G11C15/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门 用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。 匹配线用作水平位线对或用于访问水平端口的信号线。 当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。 此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。
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公开(公告)号：US07463501B2
公开(公告)日：2008-12-09
申请号：US11517441
申请日：2006-09-08
IPC分类号： G11C7/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门 用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。 匹配线用作水平位线对或用于访问水平端口的信号线。 当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。 此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。
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公开(公告)号：US06418067B1
公开(公告)日：2002-07-09
申请号：US09592454
申请日：2000-06-09
申请人： Naoya Watanabe , Akira Yamazaki , Kazutami Arimoto , Takeshi Fujino , Isamu Hayashi , Hideyuki Noda
发明人： Naoya Watanabe , Akira Yamazaki , Kazutami Arimoto , Takeshi Fujino , Isamu Hayashi , Hideyuki Noda
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C11/4076 , G11C29/846
摘要： Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.
摘要翻译： 读取数据线对，写入数据线对，备用读取数据线对和备用写入数据线对，提供在存储单元阵列上的列方向上延伸。 通过替换数据线对执行备用位修复。 列冗余控制电路改变用于输出数据写入模式和数据读取模式的备用确定结果的定时。 提供一种适于与逻辑并入并能够降低电流消耗并实现更高操作频率的半导体存储器件。
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公开(公告)号：US20100179976A1
公开(公告)日：2010-07-15
申请号：US12687756
申请日：2010-01-14
申请人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
发明人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
CPC分类号： G06F7/5235 , G06F7/5324 , G06F7/5338
摘要： A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.
摘要翻译： 半导体器件包括：解码器，接收根据布斯（Booth）算法的3比特的第一乘法器数据，指示乘法器输出移位标志，反转标志和操作标志，第一部分乘积计算单元接收2位的第一被乘数数据 指示被乘数，移位标志，反转标志和操作标志，以基于移位标志来选择第一被乘数数据的高位位和低位位之一，基于该选择位反转或非反转所选位 反转标志，基于操作标志选择反相或非反相数据和预定逻辑电平的数据之一，并将选择的数据作为指示第一乘法器数据和第一被乘数数据的部分乘积的部分乘积数据输出。
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