利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

168 条记录 (耗时 0.032 秒)

    Semiconductor memory device suitable for merging with logic
    1.
    发明授权
    Semiconductor memory device suitable for merging with logic 失效
    半导体存储器件适用于与逻辑电路合并

    公开(公告)号：US06418067B1

    公开(公告)日：2002-07-09

    申请号：US09592454

    申请日：2000-06-09

    申请人： Naoya Watanabe ,  Akira Yamazaki ,  Kazutami Arimoto ,  Takeshi Fujino ,  Isamu Hayashi ,  Hideyuki Noda

    发明人： Naoya Watanabe ,  Akira Yamazaki ,  Kazutami Arimoto ,  Takeshi Fujino ,  Isamu Hayashi ,  Hideyuki Noda

    IPC分类号： G11C700

    CPC分类号： G11C29/78 ,  G11C11/4076 ,  G11C29/846

    摘要： Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.

    摘要翻译： 读取数据线对，写入数据线对，备用读取数据线对和备用写入数据线对，提供在存储单元阵列上的列方向上延伸。 通过替换数据线对执行备用位修复。 列冗余控制电路改变用于输出数据写入模式和数据读取模式的备用确定结果的定时。 提供一种适于与逻辑并入并能够降低电流消耗并实现更高操作频率的半导体存储器件。

    Semiconductor memory device having row-related circuit operating at high speed
    2.
    发明授权
    Semiconductor memory device having row-related circuit operating at high speed 失效
    具有行相关电路的半导体存储器件以高速工作

    公开(公告)号：US06507532B1

    公开(公告)日：2003-01-14

    申请号：US09722687

    申请日：2000-11-28

    申请人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    发明人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    IPC分类号： G11C800

    CPC分类号： G11C8/12 ,  G11C8/18 ,  G11C11/4087

    摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

    摘要翻译： 中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号 时钟周期，用于传输到每个存储器子块。 备用确定电路与时钟信号异步地执行备用确定。 可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

    Semiconductor memory device including a plurality of memory blocks arranged in rows and columns
    3.
    发明授权
    Semiconductor memory device including a plurality of memory blocks arranged in rows and columns 失效
    半导体存储器件包括以行和列排列的多个存储块

    公开(公告)号：US06404695B1

    公开(公告)日：2002-06-11

    申请号：US09877026

    申请日：2001-06-11

    申请人： Takeshi Fujino ,  Akira Yamazaki

    发明人： Takeshi Fujino ,  Akira Yamazaki

    IPC分类号： G11C800

    CPC分类号： G11C11/4087

    摘要： A DRAM includes two main column selecting lines provided at each sense amplifier zone, eight sub column selecting lines provided at each sense amplifier zone to correspond to each memory block, two sub decoder column selecting lines provided at each sub decoder zone, a sub column decoder provided at each crossing portion of the sense amplifier zone and the sub decoder zone to select one sub column selecting line from corresponding eight sub column selecting lines in accordance with a signal from the two main column selecting lines and the two sub decoder column selecting lines. The area of the sense amplifier zone can be reduced compared to that of a conventional DRAM in which all signal lines for column selection were provided at a sense amplifier zone.

    摘要翻译： DRAM包括在每个读出放大器区域提供的两个主列选择线，在每个读出放大器区域处提供的八个子列选择线，以对应于每个存储块，在每个子解码器区提供的两个子解码器列选择线，子列解码器 设置在感测放大器区域和子解码器区域的每个交叉部分处，以根据来自两个主列选择线和两个子解码器列选择线的信号从相应的八个子列选择线中选择一个子列选择线。 与传统DRAM相比，读出放大器区域的面积可以减少，其中用于列选择的所有信号线都设置在读出放大器区域。

    Semiconductor memory device having delay circuit for controlling timing of internal control signal
    4.
    发明授权
    Semiconductor memory device having delay circuit for controlling timing of internal control signal 有权
    具有用于控制内部控制信号定时的延迟电路的半导体存储器件

    公开(公告)号：US06108249A

    公开(公告)日：2000-08-22

    申请号：US227938

    申请日：1999-01-11

    申请人： Isamu Hayashi ,  Akira Yamazaki

    发明人： Isamu Hayashi ,  Akira Yamazaki

    IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C7/22 ,  G11C11/401 ,  G11C7/00

    CPC分类号： G11C7/222 ,  G11C5/147 ,  G11C7/22

    摘要： An output buffer receives a voltage from a first power supply pin receiving an external power supply voltage for operation. Delay circuits included in an array control circuit, a read control circuit, a write control circuit and an internal clock generation circuit receive a voltage from a second power supply pin receiving the external power supply voltage for operation. Thus, a timing control is accurately performed for reading/writing a data signal without being affected by the change in power supply voltage due to an operation of the output buffer.

    摘要翻译： 输出缓冲器从接收用于操作的外部电源电压的第一电源引脚接收电压。 包括在阵列控制电路中的延迟电路，读控制电路，写控制电路和内部时钟产生电路接收来自接收外部电源电压的第二电源引脚的电压进行操作。 因此，由于输出缓冲器的操作而不受电源电压变化的影响，精确地执行用于读/写数据信号的定时控制。

    Semiconductor integrated circuit device with test data output nodes for parallel test results output
    5.
    发明授权
    Semiconductor integrated circuit device with test data output nodes for parallel test results output 失效
    半导体集成电路器件具有测试数据输出节点，用于并行测试结果输出

    公开(公告)号：US07047461B2

    公开(公告)日：2006-05-16

    申请号：US10322676

    申请日：2002-12-19

    申请人： Akira Yamazaki ,  Takeshi Fujino ,  Atsuo Mangyo

    发明人： Akira Yamazaki ,  Takeshi Fujino ,  Atsuo Mangyo

    IPC分类号： G11C29/00

    CPC分类号： G11C29/1201 ,  G11C29/24

    摘要： A semiconductor integrated circuit device includes test data output nodes arranged in a width of a plurality of bits and an internal data bus, greater in bit width than the test data output nodes, for transferring internal data. A predetermined number of bits of the internal data on the internal data bus are compared with bits of test expected value data equal in bit width to the test data output nodes for each bit. The predetermined number of bits of the internal data are selected in accordance with a test address signal. The bits selected is compared with the respective bits of the test expected valued data. Data indicating respective comparison results are output to the test data output nodes in parallel.

    摘要翻译： 半导体集成电路器件包括以多个位宽度布置的测试数据输出节点和内部数据总线，其位宽比测试数据输出节点更大，用于传送内部数据。 将内部数据总线上的内部数据的预定数量的比特与针对每个比特的测试数据输出节点的比特宽度相等的测试期望值数据的比特进行比较。 根据测试地址信号选择内部数据的预定位数。 所选择的比较与测试期望值数据的各个比特。 指示各个比较结果的数据被并行地输出到测试数据输出节点。

    Clock synchronous memory embedded semiconductor integrated circuit device
    6.
    发明授权
    Clock synchronous memory embedded semiconductor integrated circuit device 有权
    时钟同步存储器嵌入式半导体集成电路器件

    公开(公告)号：US5991232A

    公开(公告)日：1999-11-23

    申请号：US143253

    申请日：1998-08-28

    申请人： Masashi Matsumura ,  Akira Yamazaki ,  Isamu Hayashi ,  Atsuo Mangyo

    发明人： Masashi Matsumura ,  Akira Yamazaki ,  Isamu Hayashi ,  Atsuo Mangyo

    IPC分类号： G01R31/28 ,  G06F11/22 ,  G06F12/16 ,  G11C11/401 ,  G11C11/407 ,  G11C29/02 ,  G11C29/14 ,  G11C29/46 ,  G11C8/00

    CPC分类号： G11C29/46 ,  G11C29/14

    摘要： A semiconductor integrated circuit device includes an SDRAM module operating in synchronization with a clock signal, a logic circuit transmitting data with the SDRAM module for effecting necessary processing, a direct memory access circuit taking in and transferring an externally applied signal in synchronization with the clock signal corresponding to an operation clock of the SDRAM module, and a selector selecting either the output signal of the logic circuit and the output signal of the direct memory access circuit in accordance with a test mode instructing signal for application to the SDRAM module. A test of a synchronous memory can be performed by externally making fast and direct access to the synchronous memory without an influence of a skew in a signal.

    摘要翻译： 半导体集成电路器件包括与时钟信号同步操作的SDRAM模块，与SDRAM模块发送数据以进行必要处理的逻辑电路，直接存储器存取电路与时钟信号同步地接收和传送外部施加的信号 对应于SDRAM模块的操作时钟，以及选择器，根据用于应用于SDRAM模块的测试模式指示信号，选择逻辑电路的输出信号和直接存储器存取电路的输出信号。 可以通过外部对同步存储器进行快速和直接的访问而不受信号中的偏斜的影响来执行同步存储器的测试。

    Semiconductor memory device for high speed data communication capable of accurate testing of pass/fail and memory system employing the same
    7.
    发明授权
    Semiconductor memory device for high speed data communication capable of accurate testing of pass/fail and memory system employing the same 失效
    用于高速数据通信的半导体存储器件，能够对通过/失败的精确测试以及采用该通道的存储器系统进行测试

    公开(公告)号：US5956349A

    公开(公告)日：1999-09-21

    申请号：US781248

    申请日：1997-01-10

    申请人： Naoya Watanabe ,  Akira Yamazaki

    发明人： Naoya Watanabe ,  Akira Yamazaki

    IPC分类号： G06F11/08 ,  G06F12/06 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  G11C29/44 ,  G11C29/48

    CPC分类号： G11C29/48 ,  G11C29/14 ,  G11C29/44

    摘要： A memory includes a built-in testing circuit for determining pass/fail of a memory portion and an identifier register for storing identification value for identifying the memory. The memory performs a testing operation according to a command provided from a controller via a send link and sends the result of that testing to a sync link. Thus, the memory controller can identify a defective memory cell. In this way, erroneous operation of the system due to a defective memory cell in a memory system can be prevented.

    摘要翻译： 存储器包括用于确定存储器部分的通过/失败的内置测试电路和用于存储用于识别存储器的识别值的标识符寄存器。 存储器根据从控制器经由发送链路提供的命令执行测试操作，并将该测试的结果发送到同步链路。 因此，存储器控制器可以识别有缺陷的存储器单元。 以这种方式，可以防止由于存储器系统中的缺陷存储器单元导致的系统的错误操作。

    Memory system capable of supporting different memory devices and a memory device used therefor
    8.
    发明授权
    Memory system capable of supporting different memory devices and a memory device used therefor 失效
    能够支持不同存储器件的存储器系统和用于其的存储器件

    公开(公告)号：US06345348B2

    公开(公告)日：2002-02-05

    申请号：US08798950

    申请日：1997-02-11

    申请人： Naoya Watanabe ,  Akira Yamazaki

    发明人： Naoya Watanabe ,  Akira Yamazaki

    IPC分类号： G06F1206

    CPC分类号： G06F12/0676

    摘要： A memory includes an ROM portion storing information specific to the memory, and transfers the stored information to a memory controller via an output buffer and a sink link. The memory controller manages the characteristics of the memory, so that a memory system can be structured utilizing memories of different characteristics.

    摘要翻译： 存储器包括存储特定于存储器的信息的ROM部分，并且经由输出缓冲器和信宿链路将存储的信息传送到存储器控制器。 存储器控制器管理存储器的特性，使得可以利用不同特性的存储器来构造存储器系统。

    Semiconductor memory device suitable for mounting mixed with logic circuit, having short cycle time in reading operation
    9.
    发明授权
    Semiconductor memory device suitable for mounting mixed with logic circuit, having short cycle time in reading operation 有权
    适用于与逻辑电路混合的半导体存储器件，在读取操作中具有短的周期时间

    公开(公告)号：US06249476B1

    公开(公告)日：2001-06-19

    申请号：US09654876

    申请日：2000-09-05

    申请人： Akira Yamazaki ,  Naoya Watanabe

    发明人： Akira Yamazaki ,  Naoya Watanabe

    IPC分类号： G11C800

    CPC分类号： G11C11/4097 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/18 ,  G11C2207/104

    摘要： The DRAM macro includes a memory array having a plurality of memory cells, a read data line pair RDL provided extending in the column direction over the memory array, a read column decoder generating a column selection signal for selectively coupling the read data line pair RDL with a plurality of sense amplifiers, and a preamplifier for amplifying potential difference generated on the read data line pair RDL. The preamplifier and the read column decoder are arranged in areas opposite to each other with the memory array placed therebetween.

    摘要翻译： DRAM宏包括具有多个存储单元的存储器阵列，在存储器阵列上沿列方向延伸的读取数据线对RDL，生成列选择信号的读列解码器，用于选择性地将读数据线对RDL与 多个读出放大器和用于放大在读取数据线对RDL上产生的电位差的前置放大器。 前置放大器和读取列解码器被布置在彼此相对的区域中，存储器阵列位于它们之间。