公开(公告)号：US20120205612A1

公开(公告)日：2012-08-16

申请号：US13454625

申请日：2012-04-24

申请人： Hideyuki TABATA ,  Eiji ITO ,  Hirofumi INOUE

发明人： Hideyuki TABATA ,  Eiji ITO ,  Hirofumi INOUE

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L27/2481 ,  G11C13/00 ,  G11C13/0009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.

摘要翻译： 非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元 线条 以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。 通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔与不同的单元阵列层中的第一或第二线连接。

公开(公告)号：US20090251940A1

公开(公告)日：2009-10-08

申请号：US12405890

申请日：2009-03-17

申请人： Eiji ITO

发明人： Eiji ITO

IPC分类号： G11C5/02 ,  H01L29/00 ,  G11C5/06 ,  G11C11/00 ,  H01L21/20 ,  G11C11/34

CPC分类号： H01L27/24 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72

摘要： A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.

摘要翻译： 布置成与多个第一字线交叉的多个位线。 在第一字线和位线的每个交叉点设置第一二极管。 第一二极管的阴极连接到第一字线之一。 配置第一二极管的第一可变电阻膜设置在第一二极管和位线的阳极之间，并且与第一二极管中的每一个配置第一存储单元，并且还与第一二极管共同使用。

公开(公告)号：US20100038617A1

公开(公告)日：2010-02-18

申请号：US12540896

申请日：2009-08-13

申请人： Shingo NAKAJIMA ,  Eiji ITO ,  Mitsuhiro NOGUCHI

发明人： Shingo NAKAJIMA ,  Eiji ITO ,  Mitsuhiro NOGUCHI

IPC分类号： H01L47/00 ,  H01L21/36

CPC分类号： H01L27/24

摘要： A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.

摘要翻译： 一种具有设置在第一绝缘体上并沿第一方向延伸的第一布线层的半导体存储器件和在第一布线层上以柱形形式设置的非易失性存储单元， 元件和可变电阻元件串联连接。 可变电阻元件的电阻值根据施加到其上的电压或电流而变化。 阻挡层设置在存储单元上并且被配置在面内方向上。 导电层设置在阻挡层上并且被配置在面内方向上。 第二绝缘体设置在第一绝缘体上并且覆盖存储单元，阻挡层和导电层的侧表面。 第二布线层设置在导电层上并沿第二方向延伸。