公开(公告)号：US09070743B2

公开(公告)日：2015-06-30

申请号：US13413952

申请日：2012-03-07

申请人： Yoshiko Kato ,  Masato Endo ,  Mitsuhiko Noda ,  Mitsuhiro Noguchi

发明人： Yoshiko Kato ,  Masato Endo ,  Mitsuhiko Noda ,  Mitsuhiro Noguchi

IPC分类号： H01L29/788 ,  H01L21/762 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L21/76229 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.

摘要翻译： 根据一个实施例，半导体存储器包括设置在半导体衬底中的存储单元阵列中的存储单元，其包括由第一隔离绝缘体围绕的第一有源区，设置在半导体中的晶体管区中的晶体管 并且其包括由第二隔离绝缘体围绕的第二有源区。 第二隔离绝缘体包括第一膜和在第一膜和第二有源区之间的第二膜，并且第一膜的上表面比第二膜的上表面更靠近半导体衬底的底部。

公开(公告)号：US08400812B2

公开(公告)日：2013-03-19

申请号：US13231510

申请日：2011-09-13

申请人： Hiroyuki Kutsukake ,  Kikuko Sugimae ,  Mitsuhiro Noguchi

发明人： Hiroyuki Kutsukake ,  Kikuko Sugimae ,  Mitsuhiro Noguchi

IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11519 ,  H01L27/11529

摘要： According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit has a transistor group. The transistor group includes a first transfer transistor belonging to the first block, a second transfer transistor belonging to the second block, and a third transfer transistor belonging to the third block. The first, second, and third transfer transistors share the other of a source and a drain of each. With regard to a direction in which either of the source and the drain is connected to the other in each of the first, second, and third transfer transistors, the directions of the adjacent transfer transistors are different from each other by 90° or 180°.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器阵列和外围电路。 存储器阵列具有多个存储单元，字线和位线，其中按照位线的顺序设置第一，第二和第三块。 外围电路具有晶体管组。 晶体管组包括属于第一块的第一转移晶体管，属于第二块的第二转移晶体管和属于第三块的第三转移晶体管。 第一，第二和第三转移晶体管共享每个的源极和漏极中的另一个。 关于源极和漏极中的任一个与第一，第二和第三转移晶体管中的每一个连接到另一个的方向，相邻的转移晶体管的方向彼此相差90°或180° 。

公开(公告)号：US20130062680A1

公开(公告)日：2013-03-14

申请号：US13413952

申请日：2012-03-07

申请人： Yoshiko KATO ,  Masato Endo ,  Mitsuhiko Noda ,  Mitsuhiro Noguchi

发明人： Yoshiko KATO ,  Masato Endo ,  Mitsuhiko Noda ,  Mitsuhiro Noguchi

IPC分类号： H01L27/105 ,  H01L21/8239

CPC分类号： H01L21/76229 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.

摘要翻译： 根据一个实施例，半导体存储器包括设置在半导体衬底中的存储单元阵列中的存储单元，其包括由第一隔离绝缘体围绕的第一有源区，设置在半导体中的晶体管区中的晶体管 并且其包括由第二隔离绝缘体围绕的第二有源区。 第二隔离绝缘体包括第一膜和在第一膜和第二有源区之间的第二膜，并且第一膜的上表面比第二膜的上表面更靠近半导体衬底的底部。

公开(公告)号：US08391065B2

公开(公告)日：2013-03-05

申请号：US12877563

申请日：2010-09-08

申请人： Mitsuhiro Noguchi

发明人： Mitsuhiro Noguchi

IPC分类号： G11C16/04 ,  H01L23/48

CPC分类号： G11C16/0483 ,  G11C16/08 ,  H01L27/11519 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor memory device includes first and second memory cell blocks and an interconnect rerouting unit provided therebetween. The first memory cell block includes first interconnects and second interconnects provided in each space between the first interconnects. The second memory cell block includes a plurality of third interconnects provided on lines extending from the first interconnects and a plurality of fourth interconnects provided on lines extending from the second interconnects. A width and a thickness of the second and fourth interconnects are smaller than a width and a thickness of the first and second interconnects. Each of the first to fourth interconnects is connected to one end of first to fourth cell units including memory cells. The interconnect rerouting unit connects one of the fourth interconnects to one of the first interconnects and connects one of the third interconnects to the second interconnects.

摘要翻译： 根据一个实施例，半导体存储器件包括第一和第二存储单元块以及设置在其间的互连重路由单元。 第一存储单元块包括设置在第一互连之间的每个空间中的第一互连和第二互连。 第二存储单元块包括设置在从第一互连线延伸的线上的多个第三互连以及设置在从第二互连延伸的线上的多个第四互连。 第二和第四互连的宽度和厚度小于第一和第二互连的宽度和厚度。 第一至第四互连中的每一个连接到包括存储单元的第一至第四单元单元的一端。 互连重路由单元将第四互连中的一个连接到第一互连中的一个，并将第三互连中的一个连接到第二互连。

公开(公告)号：US08357966B2

公开(公告)日：2013-01-22

申请号：US12884764

申请日：2010-09-17

申请人： Aya Minemura ,  Kenji Sawamura ,  Mitsuhiro Noguchi

发明人： Aya Minemura ,  Kenji Sawamura ,  Mitsuhiro Noguchi

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L29/78 ,  H01L21/76232

摘要： According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction.

摘要翻译： 根据一个实施例，半导体器件包括沿着第一方向延伸的有源区域，位于有源区域的第一部分上的接触插塞和位于与有源区域中的有源区域的第一部分相邻的第二部分的晶体管 第一个方向 第一部分的垂直于第一方向的第二方向的顶表面积的宽度小于第二部分在第二方向上的顶表面积的宽度。

公开(公告)号：US08268686B2

公开(公告)日：2012-09-18

申请号：US13170592

申请日：2011-06-28

申请人： Mitsuhiro Noguchi ,  Minori Kajimoto

发明人： Mitsuhiro Noguchi ,  Minori Kajimoto

IPC分类号： H01L21/336

CPC分类号： H01L27/11546 ,  H01L27/105 ,  H01L27/11526

摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.

摘要翻译： 非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱 ，其包括围绕第一阱的侧部区域的第一部分和围绕第一阱的下部区域的第二部分，并且将第一阱与半导体衬底以及第二导电类型的第三阱电隔离， 其形成在半导体衬底中。 第三井具有比第二井的第二部分更少的深度。

公开(公告)号：US20120193698A1

公开(公告)日：2012-08-02

申请号：US13234644

申请日：2011-09-16

申请人： Mitsuhiko NODA ,  Hiroyuki Kutsukake ,  Mitsuhiro Noguchi

发明人： Mitsuhiko NODA ,  Hiroyuki Kutsukake ,  Mitsuhiro Noguchi

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11543 ,  H01L29/42324

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括元件区域，栅极绝缘膜，第一栅极电极，栅极间绝缘膜，第二栅极电极和元件隔离区域。 栅极绝缘膜形成在元件区域上。 第一栅电极形成在栅极绝缘膜上。 栅极绝缘膜形成在第一栅电极上并具有开口。 第二栅电极形成在栅间绝缘膜上并经由开口与第一栅电极接触。 元件隔离区域包围由元件区域，栅极绝缘膜和第一栅极电极形成的层叠结构。 在元件隔离区域和元件区域，栅极绝缘膜和第一栅极电极的侧表面之间形成气隙。

公开(公告)号：US20120178229A1

公开(公告)日：2012-07-12

申请号：US13426664

申请日：2012-03-22

申请人： Yoshiko KATO ,  Mitsuhiro Noguchi

发明人： Yoshiko KATO ,  Mitsuhiro Noguchi

IPC分类号： H01L21/8239

CPC分类号： H01L21/26586 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.

摘要翻译： 半导体存储器件包括第一有源区，第二有源区，第一元件隔离区和第二元件隔离区。 第一有源区形成在半导体衬底中。 第二有源区形成在半导体衬底中。 第一元件隔离区域使彼此相邻的第一有源区域电隔离。 第二元件隔离区域将彼此相邻的第二有源区域电隔离。 与第二元件隔离区域的侧面接触的第二有源区域的一部分中的杂质浓度高于第二有源区域的中心部分的杂质浓度，第一有源区域的一部分中的杂质浓度在 与第一元件隔离区域的侧面的接触与第一有源区域中的相同。

公开(公告)号：US20120151301A1

公开(公告)日：2012-06-14

申请号：US13176030

申请日：2011-07-05

申请人： Tatsuo IZUMI ,  Mitsuhiro Noguchi

发明人： Tatsuo IZUMI ,  Mitsuhiro Noguchi

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/2909 ,  G06F11/1048 ,  H03M13/2903 ,  H03M13/3715

摘要： This memory includes: bit lines; word lines crossing the bit lines; a memory cell array including memory cells provided to correspond to intersections between the bit lines and the word lines, respectively. A sense amplifier is connected to the bit lines and detects data stored in the memory cells. A word line driver controls a voltage of the word lines. An error-correcting unit includes a first error-correcting circuit having a first error-correcting capability and a second error-correcting circuit having a second error-correcting capability. The memory cells connected to each of the word lines in the memory cell block constitute a page. The error-correcting unit drives one of or both of the first and second error-correcting circuits during a data read operation or a data write operation according to a step count which is number of times of stepping up the voltage of the word lines during the data write operation.

摘要翻译： 这个内存包括：位线; 字线穿过位线; 存储单元阵列包括分别提供以对应于位线和字线之间的交点的存储单元。 感测放大器连接到位线并检测存储在存储单元中的数据。 字线驱动器控制字线的电压。 误差校正单元包括具有第一纠错能力的第一纠错电路和具有第二纠错能力的第二纠错电路。 连接到存储器单元块中的每个字线的存储单元构成一页。 在数据读取操作或数据写入操作期间，误差校正单元驱动第一和第二纠错电路中的一个或两个，根据作为在该期间的字线的电压升高的次数的步数 数据写入操作。

公开(公告)号：US20110233622A1

公开(公告)日：2011-09-29

申请号：US12884764

申请日：2010-09-17

申请人： Aya Minemura ,  Kenji Sawamura ,  Mitsuhiro Noguchi

发明人： Aya Minemura ,  Kenji Sawamura ,  Mitsuhiro Noguchi

IPC分类号： H01L29/78 ,  H01L21/76

CPC分类号： H01L29/78 ,  H01L21/76232

摘要： According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction.

摘要翻译： 根据一个实施例，半导体器件包括沿着第一方向延伸的有源区域，位于有源区域的第一部分上的接触插塞和位于与有源区域中的有源区域的第一部分相邻的第二部分的晶体管 第一个方向 第一部分的垂直于第一方向的第二方向的顶表面积的宽度小于第二部分在第二方向上的顶表面积的宽度。