公开(公告)号：US08044703B2

公开(公告)日：2011-10-25

申请号：US12109091

申请日：2008-04-24

申请人： Hiroaki Kenjyo ,  Tadashi Miyazaki ,  Yasushi Goto ,  Naotaka Oda ,  Toshifumi Sato

发明人： Hiroaki Kenjyo ,  Tadashi Miyazaki ,  Yasushi Goto ,  Naotaka Oda ,  Toshifumi Sato

IPC分类号： G06F11/16

CPC分类号： G06F11/183

摘要： Each of APRM units equipped for each of the diversity channels has printed circuit boards having circuit patterns thereon and a circuit description elements installed on the printed circuit board. The circuit description elements are FPGA elements manufactured by mutually different providers for example and implemented an electric circuit described in a hardware description language by a configuration tool. The circuit description elements can be implemented mutually different descriptions of the electric circuit, or can be implemented the electric circuit by mutually different configuration tools. Also, the printed circuit boards for the diversity channels can be different from each other.

摘要翻译： 为每个分集通道配备的每个APRM单元具有其上具有电路图案的印刷电路板和安装在印刷电路板上的电路描述元件。 电路描述元件是由相互不同的提供商制造的FPGA元件，并且通过配置工具实现了以硬件描述语言描述的电路。 电路描述元件可以实现相互不同的电路描述，或者可以通过相互不同的配置工具来实现电路。 此外，用于分集通道的印刷电路板可以彼此不同。

公开(公告)号：US20090315614A1

公开(公告)日：2009-12-24

申请号：US12109091

申请日：2008-04-24

申请人： Hiroaki KENJYO ,  Tadashi Miyazaki ,  Yasushi Goto ,  Naotaka Oda ,  Toshifumi Sato

发明人： Hiroaki KENJYO ,  Tadashi Miyazaki ,  Yasushi Goto ,  Naotaka Oda ,  Toshifumi Sato

IPC分类号： G06F11/16

CPC分类号： G06F11/183

摘要： Each of APRM units equipped for each of the diversity channels has printed circuit boards having circuit patterns thereon and a circuit description elements installed on the printed circuit board. The circuit description elements are FPGA elements manufactured by mutually different providers for example and implemented an electric circuit described in a hardware description language by a configuration tool. The circuit description elements can be implemented mutually different descriptions of the electric circuit, or can be implemented the electric circuit by mutually different configuration tools. Also, the printed circuit boards for the diversity channels can be different from each other.

摘要翻译： 为每个分集通道配备的每个APRM单元具有其上具有电路图案的印刷电路板和安装在印刷电路板上的电路描述元件。 电路描述元件是由相互不同的提供商制造的FPGA元件，并且通过配置工具实现了以硬件描述语言描述的电路。 电路描述元件可以实现相互不同的电路描述，或者可以通过相互不同的配置工具来实现电路。 此外，用于分集通道的印刷电路板可以彼此不同。

公开(公告)号：US20100254504A1

公开(公告)日：2010-10-07

申请号：US12569123

申请日：2009-09-29

申请人： Hirotaka SAKAI ,  Naotaka Oda ,  Tadashi Miyazaki ,  Toshifumi Sato

发明人： Hirotaka SAKAI ,  Naotaka Oda ,  Tadashi Miyazaki ,  Toshifumi Sato

IPC分类号： G21C17/108

CPC分类号： G21C17/108

摘要： The power monitoring system has: a local power range monitor (LPRM) unit that has a plurality of local power channels to obtain local neutron distribution in a nuclear reactor core; an averaged power range monitor (APRM) unit that receives power output signals from the LPRM unit and obtains average output power signal of the reactor core as a whole; and an oscillation power range monitor (OPRM) unit that receives the power output signals from the LPRM unit and monitors power oscillations of the reactor core. The output signals from the LPRM unit to the APRM unit and the output signals from the LPRM unit to the OPRM unit are independent.

摘要翻译： 功率监测系统具有：具有多个局部功率通道以在核反应堆堆芯中获得局部中子分布的局部功率范围监视器（LPRM）单元; 平均功率范围监视器（APRM）单元，其从LPRM单元接收功率输出信号，并获得整个反应堆堆芯的平均输出功率信号; 以及振荡功率范围监视器（OPRM）单元，其接收来自LPRM单元的功率输出信号并监测反应堆堆芯的功率振荡。 从LPRM单元到APRM单元的输出信号和从LPRM单元到OPRM单元的输出信号是独立的。

公开(公告)号：US20090164955A1

公开(公告)日：2009-06-25

申请号：US12372518

申请日：2009-02-17

申请人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

发明人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.

摘要翻译： 提供了一种用于验证包括具有多个功能元件的可编程逻辑器件的安全装置的验证方法。 验证方法包括以下步骤：在实际硬件上彻底验证多个功能元件，生成与使用预定的硬件描述语言在实际装置上验证的功能元件中的一个功能元件相同的功能元件，独立地逻辑合成每个产生的功能元件 功能元件组合成多个第一网络列表，使用预定的硬件描述语言在功能元件之间生成连接功能，将生成的连接功能逻辑合成到与连接功能相对应的第二网络列表中，将第一网络列表与 第二网络列表以产生第三网络列表，基于第三网络列表将逻辑电路写入可编程逻辑设备，以及验证实际的可编程逻辑设备。

公开(公告)号：US07669090B2

公开(公告)日：2010-02-23

申请号：US11419051

申请日：2006-05-18

申请人： Hideyuki Kitazono ,  Toshifumi Sato ,  Naotaka Oda ,  Toshiaki Ito ,  Mikio Izumi

发明人： Hideyuki Kitazono ,  Toshifumi Sato ,  Naotaka Oda ,  Toshiaki Ito ,  Mikio Izumi

IPC分类号： G01R31/28 ,  G11C29/00 ,  G01R31/26 ,  G06F11/00

CPC分类号： G01R31/317

摘要： An apparatus for verifying a custom IC including a test pattern generating unit for generating a test pattern for verifying a function of the custom IC. The test pattern is output to a master IC and a test IC. The apparatus further includes a comparing unit connected to receive operation signals output from the master IC and the test IC for comparing the operation signals to see if the operation signals are agreed with each other and for generating a comparison signal based on a comparison result, a judging unit connected to receive the comparison signal for judging if there is any abnormality in the test IC and for outputting a judged signal based on a judged result, and a computer connected to receive the judged signal for displaying the judged result of the test IC.

摘要翻译： 一种用于验证定制IC的装置，包括用于生成用于验证定制IC的功能的测试图案的测试图案生成单元。 测试模式输出到主IC和测试IC。 该装置还包括一个比较单元，连接到接收从主IC输出的操作信号和测试IC，用于比较操作信号，以观察操作信号是否彼此一致，并根据比较结果生成比较信号 连接的判断单元接收比较信号，以判断测试IC中是否存在异常，并根据判断结果输出判断信号;以及计算机，连接以接收用于显示测试IC的判断结果的判断信号。

公开(公告)号：US20070271489A1

公开(公告)日：2007-11-22

申请号：US11419051

申请日：2006-05-18

申请人： Hideyuki Kitazono ,  Toshifumi Sato ,  Naotaka Oda ,  Toshiaki Ito ,  Mikio Izumi

发明人： Hideyuki Kitazono ,  Toshifumi Sato ,  Naotaka Oda ,  Toshiaki Ito ,  Mikio Izumi

IPC分类号： G01R31/28

CPC分类号： G01R31/317

摘要： An apparatus for verifying a custom IC including a test pattern generating unit for generating a test pattern for verifying a function of the custom IC. The test pattern is output to a master IC and a test IC. The apparatus further includes a comparing unit connected to receive operation signals output from the master IC and the test IC for comparing the operation signals to see if the operation signals are agreed with each other and for generating a comparison signal based on a comparison result, a judging unit connected to receive the comparison signal for judging if there is any abnormality in the test IC and for outputting a judged signal based on a judged result, and a computer connected to receive the judged signal for displaying the judged result of the test IC.

摘要翻译： 一种用于验证定制IC的装置，包括用于生成用于验证定制IC的功能的测试图案的测试图案生成单元。 测试模式输出到主IC和测试IC。 该装置还包括一个比较单元，连接到接收从主IC输出的操作信号和测试IC，用于比较操作信号，以观察操作信号是否彼此一致，并根据比较结果生成比较信号 连接的判断单元接收比较信号，以判断测试IC中是否存在异常，并根据判断结果输出判断信号;以及计算机，连接以接收用于显示测试IC的判断结果的判断信号。

公开(公告)号：US20090055784A1

公开(公告)日：2009-02-26

申请号：US11360617

申请日：2006-02-24

申请人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

发明人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.

公开(公告)号：US20070185700A1

公开(公告)日：2007-08-09

申请号：US10591433

申请日：2005-03-04

申请人： Mikio Izumi ,  Toshifumi Hayashi ,  Teruji Tarumi ,  Shigeru Odanaka ,  Naotaka Oda ,  Toshiaki Ito ,  Toshifumi Sato ,  Hideyuki Kitazono ,  Tatsuyuki Maekawa

发明人： Mikio Izumi ,  Toshifumi Hayashi ,  Teruji Tarumi ,  Shigeru Odanaka ,  Naotaka Oda ,  Toshiaki Ito ,  Toshifumi Sato ,  Hideyuki Kitazono ,  Tatsuyuki Maekawa

IPC分类号： G06F17/50

CPC分类号： G21D3/04 ,  G21C17/00 ,  G21Y2002/50 ,  G21Y2004/30 ,  G21Y2004/40 ,  Y02E30/39

摘要： A safety protection instrumentation system for a nuclear reactor is constructed by using a digital logic, in which the digital logic includes functional units in which output logic patterns corresponding to all input logic patterns are verified in advance and a functional module formed by combining the functional units.

摘要翻译： 通过使用数字逻辑来构造核反应堆的安全保护仪表系统，其中数字逻辑包括其中预先对与所有输入逻辑模式相对应的输出逻辑模式的功能单元和通过组合功能单元形成的功能模块 。

公开(公告)号：US07774187B2

公开(公告)日：2010-08-10

申请号：US10591433

申请日：2005-03-04

申请人： Mikio Izumi ,  Toshifumi Hayashi ,  Teruji Tarumi ,  Shigeru Odanaka ,  Naotaka Oda ,  Toshiaki Ito ,  Toshifumi Sato ,  Hideyuki Kitazono ,  Tatsuyuki Maekawa

发明人： Mikio Izumi ,  Toshifumi Hayashi ,  Teruji Tarumi ,  Shigeru Odanaka ,  Naotaka Oda ,  Toshiaki Ito ,  Toshifumi Sato ,  Hideyuki Kitazono ,  Tatsuyuki Maekawa

IPC分类号： G06F9/45

CPC分类号： G21D3/04 ,  G21C17/00 ,  G21Y2002/50 ,  G21Y2004/30 ,  G21Y2004/40 ,  Y02E30/39

摘要： A safety protection instrumentation system for a nuclear reactor is constructed by using digital logic. The digital logic includes functional units in which output logic patterns corresponding to all input logic patterns are verified in advance and a functional module formed by combining the functional units.

摘要翻译： 使用数字逻辑构建核反应堆安全保护仪表系统。 数字逻辑包括其中预先对与所有输入逻辑模式相对应的输出逻辑模式的功能单元和通过组合功能单元形成的功能模块。

公开(公告)号：US07512917B2

公开(公告)日：2009-03-31

申请号：US11360617

申请日：2006-02-24

申请人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

发明人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.

摘要翻译： 提供了一种用于验证包括具有多个功能元件的可编程逻辑器件的安全装置的验证方法。 验证方法包括以下步骤：在实际硬件上彻底验证多个功能元件，生成与使用预定的硬件描述语言在实际装置上验证的功能元件中的一个功能元件相同的功能元件，独立地逻辑合成每个产生的功能元件 功能元件组合成多个第一网络列表，使用预定的硬件描述语言在功能元件之间生成连接功能，将生成的连接功能逻辑合成到与连接功能相对应的第二网络列表中，将第一网络列表与 第二网络列表以产生第三网络列表，基于第三网络列表将逻辑电路写入可编程逻辑设备，以及验证实际的可编程逻辑设备。