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公开(公告)号：US09083476B2
公开(公告)日：2015-07-14
申请号：US13980570
申请日：2012-01-20
CPC分类号： H04J3/0635 , H03L7/0805 , H03L7/18 , H03L2207/06 , H04L7/0083 , H04L7/0276 , H04L7/033
摘要： A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4).
摘要翻译： 信号复用装置包括：选择器（1），其选择输入数据（4）和互补信号（16）中的一个;时钟恢复电路（30a），其将恢复的时钟（7）的相位调整到 选择器（1）的输出信号和基于恢复的时钟（7）执行选择器（1）的输出信号的识别/恢复的触发器电路（3）。 互补信号（16）的频率是恢复时钟（7）的频率的整数倍。 选择器（1）在输入数据（4）的无信号周期的一部分期间选择互补信号（16）。
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公开(公告)号：US20130294464A1
公开(公告)日：2013-11-07
申请号：US13980570
申请日：2012-01-20
IPC分类号： H04J3/06
CPC分类号： H04J3/0635 , H03L7/0805 , H03L7/18 , H03L2207/06 , H04L7/0083 , H04L7/0276 , H04L7/033
摘要： A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4).
摘要翻译： 信号复用装置包括：选择器（1），其选择输入数据（4）和互补信号（16）中的一个;时钟恢复电路（30a），其将恢复的时钟（7）的相位调整到 选择器（1）的输出信号和基于恢复的时钟（7）执行选择器（1）的输出信号的识别/恢复的触发器电路（3）。 互补信号（16）的频率是恢复时钟（7）的频率的整数倍。 选择器（1）在输入数据（4）的无信号周期的一部分期间选择互补信号（16）。
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公开(公告)号：US07054403B2
公开(公告)日：2006-05-30
申请号：US09979254
申请日：2001-03-21
IPC分类号： H03D3/24
摘要： A phase lock circuit has a signal path to which a phase comparator, a loop filter and a voltage control oscillator are connected in series, the phase comparator being adapted to compare the phase of an input signal VIN with the phase in the output signal of the voltage control oscillator and to output its result of comparison, the loop filter being adapted to receive the output signal of the phase comparator and to output a DC voltage; the voltage control oscillator being adapted to control the output oscillation frequency depending on the DC output voltage of the loop filter, the phase lock circuit further comprising voltage tracking means for adding, to the voltage of the signal path, a signal causing the average voltage in the output voltage of the phase comparator to coincide with a predetermined reference voltage, whereby the voltage tracking means can enlarge the lock range in the phase lock circuit.
摘要翻译： 锁相电路具有相位比较器，环路滤波器和压控振荡器串联连接的信号路径，该相位比较器适于将输入信号V IN IN的相位与 电压控制振荡器的输出信号的相位并输出其比较结果，环路滤波器适于接收相位比较器的输出信号并输出直流电压; 所述电压控制振荡器适于根据所述环路滤波器的直流输出电压来控制所述输出振荡频率，所述锁相电路还包括电压跟踪装置，用于将所述信号路径的电压加到所述信号路径的电压中， 相位比较器的输出电压与预定的参考电压一致，由此电压跟踪装置可以扩大锁相电路中的锁定范围。
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公开(公告)号：US07557674B2
公开(公告)日：2009-07-07
申请号：US11587287
申请日：2006-03-07
申请人： Hideki Kamitsuna
发明人： Hideki Kamitsuna
CPC分类号： H01P1/15
摘要： Four SP4T switches (31-34) are grouped in twos to form two switch pairs. First conductive lines (411-414, 421-424) are arranged in fours between the SP4T switches (31, 34; 32, 33) constituting the switch pairs. Each of four second conductive lines (51-54) connects to a corresponding one of different conductive lines of the first conductive lines which connect to the respective switch pairs. The first and second conductive lines are arranged on a dielectric layer having a lower surface on which a ground conductor (6) is formed. The dielectric, layer has a two-layer structure. The first conductive lines are arranged on the first dielectric layer as a lower layer. The second conductive lines are arranged on the second dielectric layer as an upper layer. This arrangement makes it possible to attain a reduction in the size of a matrix switch and a reduction in loss and allow broadband operation.
摘要翻译： 四个SP4T开关（31-34）分成两组，形成两个开关对。 构成开关对的SP4T开关（31,34,32,33）之间的第一导线（411-414,421-424）被布置成四个。 四个第二导线（51-54）中的每一个连接到连接到各个开关对的第一导线的不同导线中的相应一个导线。 第一和第二导线布置在具有形成有接地导体（6）的下表面的电介质层上。 电介质层具有两层结构。 第一导电线被布置在作为下层的第一介电层上。 第二导线布置在作为上层的第二电介质层上。 这种布置使得可以实现矩阵开关的尺寸的减小和损耗的减少并允许宽带操作。
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公开(公告)号：US20070241837A1
公开(公告)日：2007-10-18
申请号：US11587287
申请日：2006-03-07
申请人： Hideki Kamitsuna
发明人： Hideki Kamitsuna
IPC分类号： H01P1/15
CPC分类号： H01P1/15
摘要： Four SP4T switches (31-34) are grouped in twos to form two switch pairs. First conductive lines (411-414, 421-424) are arranged in fours between the SP4T switches (31, 34; 32, 33) constituting the switch pairs. Each of four second conductive lines (51-54) connects to a corresponding one of different conductive lines of the first conductive lines which connect to the respective switch pairs. The first and second conductive lines are arranged on a dielectric layer having a lower surface on which a ground conductor (6) is formed. The dielectric, layer has a two-layer structure. The first conductive lines are arranged on the first dielectric layer as a lower layer. The second conductive lines are arranged on the second dielectric layer as an upper layer. This arrangement makes it possible to attain a reduction in the size of a matrix switch and a reduction in loss and allow broadband operation.
摘要翻译： 四个SP4T开关（3个1到3个4）被分组成两对以形成两个开关对。 第一导电线（4-11-11-14，4,21-2-4）排列在 构成开关对的SP4T开关（3×1 3，3×4 3 3 3 3 3 3 3 3）。 四个第二导线中的每一个连接到连接到各个开关对的第一导线的不同导线中的相应一个导线。 第一和第二导线布置在具有形成有接地导体（6）的下表面的电介质层上。 电介质层具有两层结构。 第一导电线被布置在作为下层的第一介电层上。 第二导线布置在作为上层的第二电介质层上。 这种布置使得可以实现矩阵开关的尺寸的减小和损耗的减少并允许宽带操作。
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