公开(公告)号：US20120249616A1

公开(公告)日：2012-10-04

申请号：US13424540

申请日：2012-03-20

申请人： Hiroaki KOMATSU ,  Masahiro Maki ,  Hiroyuki Abe

发明人： Hiroaki KOMATSU ,  Masahiro Maki ,  Hiroyuki Abe

IPC分类号： G09G5/10

CPC分类号： G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0233

摘要： A display device includes a plurality of gate lines, a plurality of data lines, a gate circuit, a driver, and a data selector circuit that includes a plurality of switch groups each of which has a time division switch and a timing adjustment switch that are connected in parallel. The data selector circuit outputs output signals from the driver, which have different polarities every one or more data lines of the plurality of data lines, to the respective data lines. Each of the time division switches and the timing adjustment switches is an NMOS transistor. The driver turns on the timing adjustment switches connected to the data lines to which positive output signals are output from the driver, earlier than the time division switches connected to the data lines to which negative output signals are output from the driver, by a predetermined period.

摘要翻译： 显示装置包括多个栅极线，多条数据线，门电路，驱动器和数据选择器电路，其包括多个开关组，每个开关组具有时分开关和定时调整开关， 并联连接 数据选择器电路将来自驱动器的输出信号输出到各个数据线，每个数据线的每一条或多条数据线具有不同的极性。 每个时分开关和定时调整开关都是一个NMOS晶体管。 在连接到从驱动器输出负输出信号的数据线的时分开关之前，驱动器接通连接到从驱动器输出正输出信号的数据线的定时调整开关，预定周期 。

公开(公告)号：US09123274B2

公开(公告)日：2015-09-01

申请号：US13356700

申请日：2012-01-24

申请人： Hiroyuki Abe ,  Masahiro Maki ,  Hideo Sato ,  Hiroaki Komatsu

发明人： Hiroyuki Abe ,  Masahiro Maki ,  Hideo Sato ,  Hiroaki Komatsu

IPC分类号： G09G3/00 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/006 ,  G09G3/3611 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2310/08

摘要： A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.

摘要翻译： 栅极信号线驱动电路包括多个基本电路，每个基本电路向门信号线输出在高信号周期期间为高电平的栅极信号，并在低信号周期期间输出低电平。 每个基本电路包括：玛瑙线高压施加电路，根据高信号周期接通，将高电压施加到栅极信号线; 栅极线路低电压施加电路，其根据低信号周期接通，以将低电压施加到栅极信号线; 以及第二栅极线低电压施加电路，其在关闭栅极线高压应用电路和接通栅极线路的低电压应用之间的至少一部分周期中接通以将低电压施加到栅极信号线 电路。

公开(公告)号：US08907993B2

公开(公告)日：2014-12-09

申请号：US13424540

申请日：2012-03-20

申请人： Hiroaki Komatsu ,  Masahiro Maki ,  Hiroyuki Abe

发明人： Hiroaki Komatsu ,  Masahiro Maki ,  Hiroyuki Abe

IPC分类号： G09G5/10 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0233

摘要： A display device includes a plurality of gate lines, a plurality of data lines, a gate circuit, a driver, and a data selector circuit that includes a plurality of switch groups each of which has a time division switch and a timing adjustment switch that are connected in parallel. The data selector circuit outputs output signals from the driver, which have different polarities every one or more data lines of the plurality of data lines, to the respective data lines. Each of the time division switches and the timing adjustment switches is an NMOS transistor. The driver turns on the timing adjustment switches connected to the data lines to which positive output signals are output from the driver, earlier than the time division switches connected to the data lines to which negative output signals are output from the driver, by a predetermined period.

摘要翻译： 显示装置包括多个栅极线，多条数据线，门电路，驱动器和数据选择器电路，其包括多个开关组，每个开关组具有时分开关和定时调整开关， 并联连接 数据选择器电路将来自驱动器的输出信号输出到各个数据线，每个数据线的每一条或多条数据线具有不同的极性。 每个时分开关和定时调整开关都是一个NMOS晶体管。 在连接到从驱动器输出负输出信号的数据线的时分开关之前，驱动器接通连接到从驱动器输出正输出信号的数据线的定时调整开关，预定周期 。

公开(公告)号：US09147496B2

公开(公告)日：2015-09-29

申请号：US13486236

申请日：2012-06-01

申请人： Hiroyuki Abe ,  Masahiro Maki ,  Hiroaki Komatsu

发明人： Hiroyuki Abe ,  Masahiro Maki ,  Hiroaki Komatsu

IPC分类号： G09G3/36 ,  G11C19/28 ,  G09G3/20

CPC分类号： G09G3/3677 ,  G09G3/20 ,  G09G3/2018 ,  G09G3/3674 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

摘要： A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.

摘要翻译： 显示装置的驱动电路包括连续布置的第一至第三输出信号线，具有连接到第二输出信号线的源极和连接到第一时钟信号线的漏极的第一晶体管和提供 当第二时钟信号变为有效电位时，对第一晶体管的栅极的非有效电位，其中向第一输出信号线和第三输出信号线输出有效电位的电路设置在与第 电路，其具有介于其间的显示区域向第二输出信号线输出有效电位，并且其中第一晶体管的栅极经由整流电路连接到第一输出信号线和第三输出信号线。

公开(公告)号：US20120306844A1

公开(公告)日：2012-12-06

申请号：US13486236

申请日：2012-06-01

申请人： Hiroyuki ABE ,  Masahiro Maki ,  Hiroaki Komatsu

发明人： Hiroyuki ABE ,  Masahiro Maki ,  Hiroaki Komatsu

IPC分类号： G06F3/038

CPC分类号： G09G3/3677 ,  G09G3/20 ,  G09G3/2018 ,  G09G3/3674 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28

摘要： A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.

摘要翻译： 显示装置的驱动电路包括连续布置的第一至第三输出信号线，具有连接到第二输出信号线的源极和连接到第一时钟信号线的漏极的第一晶体管和提供 当第二时钟信号变为有效电位时，对第一晶体管的栅极的非有效电位，其中向第一输出信号线和第三输出信号线输出有效电位的电路设置在与第 电路，其具有介于其间的显示区域向第二输出信号线输出有效电位，并且其中第一晶体管的栅极经由整流电路连接到第一输出信号线和第三输出信号线。

公开(公告)号：US20120188220A1

公开(公告)日：2012-07-26

申请号：US13356700

申请日：2012-01-24

申请人： Hiroyuki ABE ,  Masahiro Maki ,  Hideo Sato ,  Hiroaki Komatsu

发明人： Hiroyuki ABE ,  Masahiro Maki ,  Hideo Sato ,  Hiroaki Komatsu

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G3/006 ,  G09G3/3611 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2310/08

摘要： A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.

摘要翻译： 栅极信号线驱动电路包括多个基本电路，每个基本电路向门信号线输出在高信号周期期间为高电平的栅极信号，并在低信号周期期间输出低电平。 每个基本电路包括：玛瑙线高压施加电路，根据高信号周期接通，将高电压施加到栅极信号线; 栅极线路低电压施加电路，其根据低信号周期接通，以将低电压施加到栅极信号线; 以及第二栅极线低电压施加电路，其在关闭栅极线高压应用电路和接通栅极线路的低电压应用之间的至少一部分周期中接通以将低电压施加到栅极信号线 电路。

公开(公告)号：US08384704B2

公开(公告)日：2013-02-26

申请号：US12634733

申请日：2009-12-10

申请人： Masahiro Maki ,  Katsumi Matsumoto ,  Hideo Sato ,  Hiroyuki Abe

发明人： Masahiro Maki ,  Katsumi Matsumoto ,  Hideo Sato ,  Hiroyuki Abe

IPC分类号： G06F3/038

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2300/0408

摘要： A liquid crystal display device which can reduce a scale of the whole counter-electrode-signal drive circuits is provided. The liquid crystal display device includes: a substrate; a plurality of counter electrodes which are formed on the substrate corresponding to pixels; a plurality of counter electrode signal lines which are formed on the substrate, are electrically made conductive with the counter electrodes, extend in the X direction, and are arranged parallel to each other in the Y direction which intersects the X direction; and counter electrode signal drive circuits having control signal outputting parts which are mounted on the substrate at a rate of one control signal outputting part for two counter electrode signal lines.

摘要翻译： 提供了能够减小整个对置电极信号驱动电路的规模的液晶显示装置。 液晶显示装置包括：基板; 多个对置电极，形成在与像素对应的基板上; 形成在基板上的多个对电极信号线通过对置电极导电，在X方向上延伸，并且在与X方向相交的Y方向上彼此平行地配置; 以及具有控制信号输出部件的对电极信号驱动电路，其以两个对电极信号线的一个控制信号输出部分的速率安装在基板上。

公开(公告)号：US08619014B2

公开(公告)日：2013-12-31

申请号：US12835815

申请日：2010-07-14

申请人： Masahiro Maki ,  Hideo Sato ,  Hiroyuki Abe

发明人： Masahiro Maki ,  Hideo Sato ,  Hiroyuki Abe

IPC分类号： G09G3/36

CPC分类号： G02F1/13306 ,  G09G3/3655 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/0297 ,  G09G2310/08

摘要： A liquid crystal display device which can reduce a circuit scale of a drive circuit is provided. A TFT substrate of the liquid crystal display device includes a pixel circuit in each pixel, and the pixel circuit includes a thin film transistor, a pixel electrode which is connected to a source side of the thin film transistor, and a common electrode which is one planar transparent electrode extending in a display region in a planar shape. A vertical drive circuit includes a transistor which is driven by a control signal voltage including a clock signal from a drive IC, and constitutes a damper for a high voltage. The drive IC outputs an equalizing switch signal voltage to equalizing switches which connect the common electrode and data signal lines.

摘要翻译： 提供了能够减小驱动电路的电路规模的液晶显示装置。 液晶显示装置的TFT基板包括每个像素中的像素电路，像素电路包括薄膜晶体管，连接到薄膜晶体管的源极侧的像素电极和作为一个的公共电极的像素电极 在平面形状的显示区域中延伸的平面状透明电极。 垂直驱动电路包括由包括来自驱动IC的时钟信号的控制信号电压驱动的晶体管，并构成用于高电压的阻尼器。 驱动IC输出均衡开关信号电压以均衡连接公共电极和数据信号线的开关。

公开(公告)号：US08456200B2

公开(公告)日：2013-06-04

申请号：US13253202

申请日：2011-10-05

申请人： Hideo Sato ,  Masahiro Maki ,  Hiroyuki Abe

发明人： Hideo Sato ,  Masahiro Maki ,  Hiroyuki Abe

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： G09G3/3677 ,  G09G3/00

摘要： Provided is a gate signal line driving circuit including: 2n clock signal lines where 2n-phase clock signals are input in the normal order of the sequence in normal-directional scanning and in the inverse order of the sequence in inverse-directional scanning, respectively; and a plurality of basic circuits, each being connected with the 2n clock signal lines and outputting a gate signal from an output terminal, in which each of the basic circuits includes a high-voltage applying switching circuit where one clock signal line is connected to an input side and applies a voltage applied to the clock signal line to the output terminal and an off-signal applying switching circuit that applies an off-voltage to a switch of the high-voltage applying switching circuit, and a clock signal line where a clock signal having an inverse phase is connected to a switch of the off-signal applying switching circuit.

摘要翻译： 提供了一种栅极信号线驱动电路，包括：2n频相位信号线，其中2n相位时钟信号分别以正向扫描中的顺序的正常顺序和逆序扫描中的顺序的逆顺序输入; 以及多个基本电路，每个基本电路均与2n个时钟信号线连接，并从输出端输出一个门信号，其中每个基本电路包括一个高电压施加开关电路，其中一个时钟信号线连接到 施加到时钟信号线的电压到输出端子，以及向高电压施加开关电路的开关施加截止电压的截止信号施加开关电路，以及时钟信号线，其中时钟 具有反相的信号连接到断开信号施加开关电路的开关。

公开(公告)号：US08384703B2

公开(公告)日：2013-02-26

申请号：US12634727

申请日：2009-12-10

申请人： Masahiro Maki ,  Hideo Sato ,  Hiroyuki Abe

发明人： Masahiro Maki ,  Hideo Sato ,  Hiroyuki Abe

IPC分类号： G06F3/038

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G2300/0408 ,  G09G2300/0434 ,  G09G2320/0219 ,  G09G2320/0223 ,  G09G2320/0247

摘要： In a liquid crystal display device which arranges a drive circuit on left and right sides of a display region in a two-split manner, flickering at an edge of a screen can be reduced. In a liquid crystal display device which arranges first and second counter electrode drive circuits on left and right sides of a display region respectively, during an arbitrary 1 frame period, a first counter electrode signal drive circuit 3L applies a first voltage to at least one counter electrode signal line portion CX1, CX3, . . . CXn−1 and a second voltage different from the first voltage to at least one counter electrode signal line portion CX1, CX3, . . . CXn−1, and a second counter electrode signal drive circuit 3R applies the first voltage to at least one counter electrode signal line portion CX2, CX4, . . . CXn and the second voltage to at least one counter electrode signal line portion CX2, CX4, . . . CXn.

摘要翻译： 在液晶显示装置中，以二分割的方式在显示区域的左侧和右侧布置驱动电路，可以减少屏幕边缘的闪烁。 在分别在显示区域的左右两侧配置第一和第二对置电极驱动电路的液晶显示装置中，在任意1帧期间，第一对置电极信号驱动电路3L向至少一个计数器施加第一电压 电极信号线部分CX1，CX3。 。 。 CXn-1和不同于第一电压的至少一个对置电极信号线部分CX1，CX3的第二电压。 。 。 CXn-1，第二对置电极信号驱动电路3R将第一电压施加到至少一个对置电极信号线部分CX2，CX4。 。 。 CXn和第二电压到至少一个对电极信号线部分CX2，CX4，...。 。 。 CXn。