公开(公告)号：US4769770A

公开(公告)日：1988-09-06

申请号：US807684

申请日：1985-12-11

申请人： Hiroo Miyadera ,  Shun Kawabe ,  Hiroshi Murayama ,  Yasuhiko Hatakeyama

发明人： Hiroo Miyadera ,  Shun Kawabe ,  Hiroshi Murayama ,  Yasuhiko Hatakeyama

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/08 ,  G06F17/16 ,  G06F9/36 ,  G06F9/00

CPC分类号： G06F12/0284

摘要： An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.

摘要翻译： 具有地址转换系统的信息处理装置包括多个处理器，每个处理器通过将逻辑地址转换为虚拟存储系统中的实际地址进行数据处理来执行寻址，用于数据处理。 多个处理器包括标量处理器，用于通过使用地址转换表将逻辑地址转换成真实地址; 以及矢量处理器，用于确定要重定位的逻辑地址是否在预定地址范围内，用于当逻辑地址位于预定地址范围内时，基于重定位表将逻辑地址重定位到实地址，并且使用 逻辑地址作为逻辑地址位于预定地址范围之外的实地址。 预定地址范围和重定位表的内容由监控程序存储区域的标量处理器设置。

公开(公告)号：US4903234A

公开(公告)日：1990-02-20

申请号：US196538

申请日：1988-05-20

申请人： Taketoshi Sakuraba ,  Hisashi Katada ,  Yoshitaka Ohfusa ,  Yasufumi Yoshizawa ,  Toshiaki Arai ,  Hiroo Miyadera

发明人： Taketoshi Sakuraba ,  Hisashi Katada ,  Yoshitaka Ohfusa ,  Yasufumi Yoshizawa ,  Toshiaki Arai ,  Hiroo Miyadera

IPC分类号： G06F12/14 ,  G06F12/02 ,  G06F12/10 ,  G11C8/06

CPC分类号： G11C8/06 ,  G06F12/023 ,  G06F12/1475 ,  G06F12/10

摘要： In a memory system having a storage device and a key storage keeping key data controlling an access to the storage device, there is disposed a key address translation structure for obtaining an address of an entry of the key storage based on an address of the storage device to which an access request is issued. As a result, when subdividing the storage device according to the key data setting unit, each subdivided area can be assigned with a variable size and a plurality of sizes are enabled to be specified for the key data setting units at the same time.

摘要翻译： 在具有控制对存储装置的访问的存储装置和密钥存储保持密钥数据的存储器系统中，设置有用于基于存储装置的地址获得密钥存储器的条目的地址的密钥地址转换结构 向其发出访问请求。 结果，当根据密钥数据设置单元细分存储设备时，可以为每个细分区域分配可变大小，并且能够同时为密钥数据设置单元指定多个大小。

公开(公告)号：US4959778A

公开(公告)日：1990-09-25

申请号：US251841

申请日：1988-09-30

申请人： Hiroo Miyadera ,  Toru Ohtsuki ,  Toshiaki Kawamura

发明人： Hiroo Miyadera ,  Toru Ohtsuki ,  Toshiaki Kawamura

IPC分类号： G06F9/355 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F9/342 ,  G06F12/0292

摘要： An address space switching apparatus has a group of conventional registers capable of storing address information and a group of additional registers capable of storing address information longer than the address information stored by the group of conventional registers. The register length of the group of additional registers is not restricted by the length of the group of conventional registers and is selected to be of a magnitude sufficient to define a desired operand address space. Information items stored in the group of additional registers such as a base address and an index value associated with the extended address space are selected when an operand address is to be generated so as to be appropriately employed for the address computation, thereby supplying address information having a length sufficient for the extended address space. On the other hand, when an address other than an operand address is to be created, information items stored in the group of conventional registers are selected so as to be utilized in the address computation.

摘要翻译： 地址空间切换装置具有能够存储地址信息的一组常规寄存器和能够存储比常规寄存器组存储的地址信息更长的地址信息的一组附加寄存器。 附加寄存器组的寄存器长度不受常规寄存器组的长度限制，并且被选择为足以限定所需操作数地址空间的量级。 当要生成操作数地址时，选择存储在附加寄存器组中的信息项，例如与扩展地址空间相关联的基址和索引值，以便适当地用于地址计算，从而提供具有 足够扩展地址空间的长度。 另一方面，当要创建除操作数地址之外的地址时，选择存储在常规寄存器组中的信息项，以便在地址计算中使用。