公开(公告)号：US4959778A

公开(公告)日：1990-09-25

申请号：US251841

申请日：1988-09-30

申请人： Hiroo Miyadera ,  Toru Ohtsuki ,  Toshiaki Kawamura

发明人： Hiroo Miyadera ,  Toru Ohtsuki ,  Toshiaki Kawamura

IPC分类号： G06F9/355 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F9/342 ,  G06F12/0292

摘要： An address space switching apparatus has a group of conventional registers capable of storing address information and a group of additional registers capable of storing address information longer than the address information stored by the group of conventional registers. The register length of the group of additional registers is not restricted by the length of the group of conventional registers and is selected to be of a magnitude sufficient to define a desired operand address space. Information items stored in the group of additional registers such as a base address and an index value associated with the extended address space are selected when an operand address is to be generated so as to be appropriately employed for the address computation, thereby supplying address information having a length sufficient for the extended address space. On the other hand, when an address other than an operand address is to be created, information items stored in the group of conventional registers are selected so as to be utilized in the address computation.

摘要翻译： 地址空间切换装置具有能够存储地址信息的一组常规寄存器和能够存储比常规寄存器组存储的地址信息更长的地址信息的一组附加寄存器。 附加寄存器组的寄存器长度不受常规寄存器组的长度限制，并且被选择为足以限定所需操作数地址空间的量级。 当要生成操作数地址时，选择存储在附加寄存器组中的信息项，例如与扩展地址空间相关联的基址和索引值，以便适当地用于地址计算，从而提供具有 足够扩展地址空间的长度。 另一方面，当要创建除操作数地址之外的地址时，选择存储在常规寄存器组中的信息项，以便在地址计算中使用。

公开(公告)号：US4543641A

公开(公告)日：1985-09-24

申请号：US461257

申请日：1983-01-26

申请人： Masaharu Fukuta ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki

发明人： Masaharu Fukuta ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki

IPC分类号： G06F7/53 ,  G06F7/491 ,  G06F7/496 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527

CPC分类号： G06F7/4915

摘要： A multiplier device comprising hold means for holding the result of addition, block product means for producing k block products each having 2n bits, where n is an integer equal to or greater than 2, the k block products being formed by multiplying each block by n bits, k blocks being obtained by dividing a multiplicand at intervals of n bits from the least significant bit of the multiplicand, and adder means for adding two groups of block products to the output of the hold means, the two groups of block products consisting of alternate block products out of the k block products from the block product means.

摘要翻译： 一种乘法器装置，包括用于保持加法结果的保持装置，用于产生每个具有2n位的k个块产物的块产生装置，其中n是等于或大于2的整数，所述k个块产物通过将每个块乘以n 比特，k个块通过以被乘数的最低有效位的n比特的间隔划分被乘数而获得，以及加法器装置，用于将两组块产物加到保持装置的输出，两组块产物由 替代块产品从块产品中获取块产品的手段。

公开(公告)号：US4603397A

公开(公告)日：1986-07-29

申请号：US462423

申请日：1983-01-31

申请人： Toru Ohtsuki ,  Yoshio Oshima ,  Sako Ishikawa ,  Masaharu Fukuta

发明人： Toru Ohtsuki ,  Yoshio Oshima ,  Sako Ishikawa ,  Masaharu Fukuta

IPC分类号： G06F7/491 ,  G06F7/493 ,  G06F7/496 ,  G06F7/508 ,  G06F7/52

CPC分类号： G06F7/4917

摘要： In preparation of addresses of a quotient prediction table used in a binary coded decimal number division scheme with predetermined bits of a dividend and a divisor in binary coded decimal representation, the addresses are modified with the redundant bits. The absolute bit number for the addresses is thus decreased, whereby data quantity and hence capacity of RAM required for implementing the quotient prediction table can be significantly reduced, while satisfactory function of the quotient prediction table being assured. The apparatus for the binary coded decimal number division is implemented inexpensively in a small size.

摘要翻译： 在用二进制编码的十进制数分割方案中使用的商数预测表的地址和二进制编码十进制表示中的除数的除数和除数的二进制编码的十进制数分割方案中，地址被修改。 因此，地址的绝对位数减少，从而可以显着地减少用于实现商预测表所需的RAM的数据量和因此的容量，同时确保商预测表的令人满意的功能。 用于二进制编码的十进制数除法的装置以小尺寸廉价地实现。

公开(公告)号：US5187802A

公开(公告)日：1993-02-16

申请号：US452240

申请日：1989-12-18

申请人： Taro Inoue ,  Hidenori Umeno ,  Toru Ohtsuki ,  Kiyoshi Ogawa

发明人： Taro Inoue ,  Hidenori Umeno ,  Toru Ohtsuki ,  Kiyoshi Ogawa

IPC分类号： G06F9/46 ,  G06F9/455 ,  G06F9/48

CPC分类号： G06F9/4812 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45579

摘要： In a virtual machine system in which a virtual machine directly executes operations by use of the hardware without an intervention from the virtual machine control program (VMCP), at an occurrence of an input/output interruption, the system sets to a storage an event that the input/output interruption has been accepted and reserved by the VMCP. When the virtual machine processes interruption information by means of the hardware without an intervention of the VMCP, the virtual machine resets the state of the storage. When the virtual machine is set to an interruptible state, control is passed to the VMCP. The VMCP tests to determine whether or not the virtual machine has reset the state of the storage, thereby judging an acceptability of the interruption.

摘要翻译： 在虚拟机系统中虚拟机通过使用硬件直接执行操作而无需来自虚拟机控制程序（VMCP）的干预，在发生输入/输出中断时，系统将存储事件设置为存储 输入/输出中断已被VMCP接受并保留。 当虚拟机在没有VMCP干预的情况下通过硬件处理中断信息时，虚拟机重置存储器的状态。 当虚拟机设置为可中断状态时，控制将传递给VMCP。 VMCP测试以确定虚拟机是否已经重置存储器的状态，从而判断中断的可接受性。

公开(公告)号：US4635220A

公开(公告)日：1987-01-06

申请号：US549809

申请日：1983-11-08

申请人： Hideaki Yabe ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki ,  Masaharu Fukuta

发明人： Hideaki Yabe ,  Yoshio Oshima ,  Sako Ishikawa ,  Toru Ohtsuki ,  Masaharu Fukuta

IPC分类号： G06F7/491 ,  G06F7/493 ,  G06F7/496 ,  G06F7/52

CPC分类号： G06F7/4917

摘要： A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted quotient read out from the quotient prediction table is used intact when the predicted quotient is correct while otherwise the predicted quotient is decremented by one, wherein the values stored in the quotient prediction table together with redundant bit are previously modified to (0110).sub.2 to (1111).sub.2 in the binary coded decimal representation. The multiple value register is selected by using three of the four bits of the modified predicted quotient, while upon determination of the quotient, the value used for modification is subtracted from the output value of the quotient prediction table to thereby derive the predicted quotient of one digit. With this arrangement, three of the four bits of the predicted quotient of one digit read out from the quotient prediction table can be used directly as the selection signal for selecting the relevant divisor multiple register.

摘要翻译： 二进制编码十进制数分割装置，其中以二进制编码十进制表示的商以逐个数字为基础通过使用商预测表和一组多值寄存器来确定，并且其中从 商预测表在预测商正确的情况下完整使用，否则预测商减1，其中存储在商预测表中的值与冗余位一起预先修改为（0110）2至（1111）2 二进制编码十进制表示。 通过使用修改的预测商的四位中的三位来选择多值寄存器，而在商确定时，从商预测表的输出值中减去用于修改的值，从而导出一个预测商的预测商 数字。 利用这种布置，从商预测表读出的一位数的预测商的四位中的三位可以直接用作选择相关除数多寄存器的选择信号。

公开(公告)号：US5499379A

公开(公告)日：1996-03-12

申请号：US8842

申请日：1993-01-25

申请人： Shunji Tanaka ,  Toru Ohtsuki ,  Hiroaki Sato ,  Hideo Sawamoto ,  Ryo Yamagata ,  Masaya Watanabe ,  Hidenori Umeno ,  Masatoshi Haraguchi

发明人： Shunji Tanaka ,  Toru Ohtsuki ,  Hiroaki Sato ,  Hideo Sawamoto ,  Ryo Yamagata ,  Masaya Watanabe ,  Hidenori Umeno ,  Masatoshi Haraguchi

IPC分类号： G06F13/10 ,  G06F9/318 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/3017 ,  G06F9/45558 ,  G06F9/4812 ,  G06F2009/45579

摘要： A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.

摘要翻译： 一种多操作系统运行系统，其中可以在一个控制程序（CP）或一个控制装置的控制下，分别在不同架构的机器上操作的多个操作系统（OS）在一个裸机上运行。 能够在与裸机相同架构的机器上运行的操作系统的输入/输出指令和输入/输出中断在裸机上直接执行，无需转换格式。 允许在转换格式的同时直接执行适用于与裸机机架不同的架构的机器上运行的操作系统的输入/输出指令和输入/输出中断。

公开(公告)号：US5101346A

公开(公告)日：1992-03-31

申请号：US413068

申请日：1989-09-27

申请人： Toru Ohtsuki

发明人： Toru Ohtsuki

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/50 ,  G06F12/08 ,  G06F15/167 ,  G06F15/177

CPC分类号： G06F15/167

摘要： A virtual machine system which includes a plurality of virtual machines by using a computer system of a multi-processor configuration having a plurality of real instruction processors and a real main storage which is divided into a plurality of storage regions to be allocated to the virtual machines, respectively. Each of the virtual machines is so organized as not to make access to the regions allocated to the other virtual machines. When one and the same virtual machine includes a plurality of real instruction processors, invalidation of entry of a buffer storage of another real instruction processor as conditioned by execution of a predetermined instruction by a real instruction processor is performed only for the other real instruction processor assigned to the same virtual machine as the real instruction processor and is inhibited from affecting the real instruction processors assigned to the other virtual machines.

摘要翻译： 一种虚拟机系统，其通过使用具有多个实际指令处理器的多处理器配置的计算机系统和被分成要分配给虚拟机的多个存储区域的实际主存储器来包括多个虚拟机 ， 分别。 每个虚拟机的组织方式如此组织，不能访问分配给其他虚拟机的区域。 当同一个虚拟机包括多个实际指令处理器时，仅对另一个实际指令处理器执行由实际指令处理器执行的预定指令调节的另一个实际指令处理器的缓冲存储器的输入的无效 到与实际指令处理器相同的虚拟机，并被禁止影响分配给其他虚拟机的实际指令处理器。

公开(公告)号：US5077654A

公开(公告)日：1991-12-31

申请号：US281334

申请日：1988-12-08

申请人： Toru Ohtsuki

发明人： Toru Ohtsuki

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F12/02 ,  G06F12/10 ,  G06F12/12

CPC分类号： G06F9/4843 ,  G06F12/0292

摘要： A virtual machine system for executing fast speed address translation in plural virtual machines having a two-stage address translation mechanism. The system permits address translation to be executed by adding to an output from a first address translation address constants in a hold apparatus holding address constants including zero, executing a second address translation, and selecting an output from the first address translation to which the address constants have been added or an output from the second address translation. An address translation for a plurality of different regions is performed by switching a value for the address constants held by the hold apparatus.

摘要翻译： 一种用于在具有两级地址转换机制的多个虚拟机中执行快速地址转换的虚拟机系统。 该系统允许通过在保持设备中的第一地址转换地址常数的输出中添加地址转换来执行地址转换，所述保持设备保存包括零的地址常数，执行第二地址转换，以及从第一地址转换中选择地址常数 已被添加或来自第二个地址转换的输出。 通过切换由保持装置保持的地址常数的值来执行多个不同区域的地址转换。

公开(公告)号：US4677583A

公开(公告)日：1987-06-30

申请号：US625131

申请日：1984-06-27

申请人： Toru Ohtsuki ,  Yoshio Oshima ,  Sako Ishikawa ,  Hideaki Yabe ,  Masaharu Fukuta

发明人： Toru Ohtsuki ,  Yoshio Oshima ,  Sako Ishikawa ,  Hideaki Yabe ,  Masaharu Fukuta

IPC分类号： G06F7/496 ,  G06F7/491 ,  G06F7/506 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527

CPC分类号： G06F7/4915

摘要： An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.

摘要翻译： 用于十进制乘法的装置将二进制编码十进制（BCD）的乘法器分成多个组，生成多个部分乘积乘以BCD的被乘数和连续循环的多组乘法器，并将它们添加到中间乘积 先前产生的部分产品的总和。 部分乘积和中间乘积的加法由进位保存加法器进行。 在第一个循环中，将中间产品设置为零，并且将中间产品和部分产品中的任一个的每个数字加到6上，并且部分产品和中间产品的添加由 连续循环中的进位保存加法器循环。 在最后一个循环中，进位保存加法器的和和进位由全加器相加，根据全加器各位的进位转移的存在，对每个数位进行6减，结果值为 输出为乘法结果。

公开(公告)号：US5437033A

公开(公告)日：1995-07-25

申请号：US787074

申请日：1991-11-04

申请人： Taro Inoue ,  Hidenori Umeno ,  Shunji Tanaka ,  Tadashi Yamamoto ,  Toru Ohtsuki

发明人： Taro Inoue ,  Hidenori Umeno ,  Shunji Tanaka ,  Tadashi Yamamoto ,  Toru Ohtsuki

IPC分类号： G06F9/46 ,  G06F9/455 ,  G06F11/00 ,  G06F11/30 ,  G06F9/00

CPC分类号： G06F9/45533 ,  G06F11/1484 ,  G06F11/1438 ,  G06F2201/815

摘要： A system and method for continuous operation of a virtual machine system having operation modes including a guest mode in which virtual machines are operated and a nonguest mode in which a virtual machine monitor for controlling the virtual machines is operated. The continuous guest is a virtual machine which does not stop executing operation at the occurrence of a failure due to program error of the virtual machine monitor. A main storage is provided with two areas. One of the two areas is a continuous guest area having the same host absolute address in the nonguest mode as a guest absolute address in the guest mode, the area is used by the continuous guest which is a virtual machine which continues to operate on transition of the operation mode from the guest mode to the nonguest mode. The other is an area in which a program module for dispatching the continuous guest in response to the transition of the operation mode from the guest mode to the nonguest mode. The continuous guest is allocated to the guest area on transition of the operation mode from the guest mode to the nonguest mode. Occurrence of a failure due to a program error of the virtual machine monitor is detected and by starting the program module for dispatching the continuous guest in response to the detection of the occurrence of the failure, the operation of the continuous guest does not stop executing.

摘要翻译： 一种用于在具有操作模式包括其中虚拟机操作的客人模式和其中被操作的虚拟机监视器，用于控制虚拟机的nonguest模式的虚拟机系统的连续运行的系统和方法。 连续的客人是在虚拟机不停止在故障发生在执行操作由于在虚拟机监视器的程序错误。 主要存储设有两个区域。 这两个区域中的一个是连续的访客区域，在访客模式中，作为访客绝对地址，在非最大模式中具有相同的主机绝对地址，该区域被连续访客使用，该连续访客是继续操作的虚拟机 从客人模式到非最终模式的操作模式。 另一个是用于响应于操作模式从访客模式转换到非最终模式而分发连续客户的程序模块的区域。 连续访客在从访客模式转换到非最终模式的过程中被分配给客户区域。 检测到由于虚拟机监视器的程序错误而导致的故障的发生，并且响应于检测到故障的发生而启动用于发送连续客户机的程序模块，连续客户机的操作不停止执行。