公开(公告)号：US20100034039A1

公开(公告)日：2010-02-11

申请号：US12458428

申请日：2009-07-13

申请人： Kenjyu Shimogawa ,  Hiroshi Furuta

发明人： Kenjyu Shimogawa ,  Hiroshi Furuta

IPC分类号： G11C7/00

CPC分类号： G11C7/1033 ,  G06F11/1044 ,  G11C7/08 ,  G11C11/4091

摘要： A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation.

摘要翻译： 半导体集成电路具有耦合到相同字线的存储器单元数量K（K是2个或更多个的自然数），以及耦合到存储单元的多个读出放大器电路。 多个读出放大器电路分为N个（N个是2个以上的自然数）组。 在N个组中，在第一组读出放大器电路被激活并执行预定的读出操作之后，激活第二组读出放大器电路并执行预定的读出操作， 读出放大器电路的第N组顺序地被激活，以执行预定的读出操作。

公开(公告)号：US08519774B2

公开(公告)日：2013-08-27

申请号：US13620803

申请日：2012-09-15

申请人： Kenjyu Shimogawa ,  Hiroshi Furuta

发明人： Kenjyu Shimogawa ,  Hiroshi Furuta

IPC分类号： H03K3/01

摘要： A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.

公开(公告)号：US08310297B2

公开(公告)日：2012-11-13

申请号：US12929753

申请日：2011-02-14

申请人： Kenjyu Shimogawa ,  Hiroshi Furuta

发明人： Kenjyu Shimogawa ,  Hiroshi Furuta

IPC分类号： H03K3/01

CPC分类号： H03K5/05 ,  H01L2924/0002 ,  H03K3/0375 ,  H03K3/356156 ,  H03K2005/00058 ,  H01L2924/00

摘要： Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.

摘要翻译： 公开了一种半导体器件，包括：模式控制电路，当待机控制信号处于激活状态时，基于来自定时器电路的定时器输出信号，生成改变功能电路部分的逻辑状态的MODE控制输出信号 以及输出控制电路，其接收所述功能电路部的输出信号，并控制所述输出信号的输出; 基于通过延迟电路延迟MODE控制输出信号而产生的延迟输出信号。 当功能电路部分通过MODE控制输出信号改变逻辑状态时，输出控制电路不将功能电路部分输出信号传送到输出，而是在功能电路部分变化之前保持并输出功能电路部分输出信号 逻辑状态由MODE控制输出信号。

公开(公告)号：US07940577B2

公开(公告)日：2011-05-10

申请号：US11592978

申请日：2006-11-06

申请人： Kenjyu Shimogawa ,  Hiroshi Furuta

发明人： Kenjyu Shimogawa ,  Hiroshi Furuta

IPC分类号： G11C7/00

CPC分类号： G11C5/14

摘要： The semiconductor integrated circuit device includes a voltage control circuit that generates a control voltage for deactivating a field effect transistor by a gate voltage. The voltage control circuit controls a voltage so as to substantially minimize the leakage current which flows when the field effect transistor is inactive with respect to a device temperature.

摘要翻译： 半导体集成电路器件包括电压控制电路，其产生用于通过栅极电压去激活场效应晶体管的控制电压。 电压控制电路控制电压，以使得当场效应晶体管相对于器件温度无效时流过的漏电流基本上最小化。

公开(公告)号：US07274616B2

公开(公告)日：2007-09-25

申请号：US11322425

申请日：2006-01-03

申请人： Hiroshi Furuta ,  Kenjyu Shimogawa ,  Ichirou Mizuguchi ,  Junji Monden ,  Shinji Takeda

发明人： Hiroshi Furuta ,  Kenjyu Shimogawa ,  Ichirou Mizuguchi ,  Junji Monden ,  Shinji Takeda

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C11/417 ,  G11C5/147

摘要： An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.

摘要翻译： 集成电路装置包括具有由格栅状布置的CMOSFET形成的多个存储单元的SRAM单元阵列。 SRAM单元阵列在1位序列中具有一对电源线和地线。 集成电路装置还包括检测器，检测每1位序列的锁存的发生并输出检测信号;以及功率控制器，其针对每个1位序列控制对电力线的电源电压。 功率控制器根据检测信号将按照1位序列提供给电力线的电压降低到锁定状态下降到预定值。

公开(公告)号：US20060164905A1

公开(公告)日：2006-07-27

申请号：US11322425

申请日：2006-01-03

申请人： Hiroshi Furuta ,  Kenjyu Shimogawa ,  Ichirou Mizuguchi ,  Junji Monden ,  Shinji Takeda

发明人： Hiroshi Furuta ,  Kenjyu Shimogawa ,  Ichirou Mizuguchi ,  Junji Monden ,  Shinji Takeda

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/147

摘要： An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.

摘要翻译： 集成电路装置包括具有由格栅状布置的CMOSFET形成的多个存储单元的SRAM单元阵列。 SRAM单元阵列在1位序列中具有一对电源线和地线。 集成电路装置还包括检测器，检测每1位序列的锁存的发生并输出检测信号;以及功率控制器，其针对每个1位序列控制对电力线的电源电压。 功率控制器根据检测信号将按照1位序列提供给电力线的电压降低到锁定状态下降到预定值。

公开(公告)号：US20050144576A1

公开(公告)日：2005-06-30

申请号：US11019634

申请日：2004-12-23

申请人： Hiroshi Furuta ,  Kenjyu Shimogawa

发明人： Hiroshi Furuta ,  Kenjyu Shimogawa

IPC分类号： G06F17/50 ,  H01L21/00 ,  H01L21/336 ,  H01L21/82

CPC分类号： G06F17/5036 ,  G06F17/5045

摘要： In one embodiment of the present invention, in a discrete MOSFET, the ZTC point is determined by combining the variation of the drain current induced by the variation of the threshold voltage in response to the temperature and the variation of the drain current induced by the variation of the mobility in response to the temperature. The chips configured with a number of circuits, however, include the circuits whose main operation regions of the MOSFETs are different. In CMOS circuits, the MOSFETs operate in the saturation region. On the other hand, in analog circuits, such as sense amplifiers or bandgap circuits, the MOSFETs operate in the linear region. In the design of the temperature dependence of the chip, the design is achieved by independently different models for respective MOSFETs whose operation regions are different.

摘要翻译： 在本发明的一个实施例中，在分立MOSFET中，通过组合由阈值电压的变化引起的漏极电流的变化响应于温度和由变化引起的漏极电流的变化来确定ZTC点 的温度响应的流动性。 然而，配置有多个电路的芯片包括MOSFET的主要操作区域不同的电路。 在CMOS电路中，MOSFET在饱和区域工作。 另一方面，在诸如读出放大器或带隙电路的模拟电路中，MOSFET在线性区域中工作。 在设计芯片的温度依赖性时，设计是通过独立不同的型号实现的，其各自的MOSFET的工作区域不同。

公开(公告)号：US08552793B2

公开(公告)日：2013-10-08

申请号：US13620803

申请日：2012-09-15

申请人： Kenjyu Shimogawa ,  Hiroshi Furuta

发明人： Kenjyu Shimogawa ,  Hiroshi Furuta

IPC分类号： H03K3/01

CPC分类号： H03K5/05 ,  H01L2924/0002 ,  H03K3/0375 ,  H03K3/356156 ,  H03K2005/00058 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.

摘要翻译： 一种半导体集成电路装置，具备包含多个场效应晶体管的功能电路部，模式控制电路，接收第一控制信号，生成用于改变功能电路部的逻辑状态的第二控制信号， 输出控制电路，其接收功能电路部分的输出信号并控制输出信号的输出;以及控制电路，其接收第二控制信号并向输出控制电路产生第三控制信号。 在功能电路部分根据第二控制信号改变逻辑状态的时间段期间，输出控制电路根据第三控制信号反转功能电路部分的输出信号。

公开(公告)号：US20130033308A1

公开(公告)日：2013-02-07

申请号：US13620803

申请日：2012-09-15

申请人： Kenjyu Shimogawa ,  Hiroshi Furuta

发明人： Kenjyu Shimogawa ,  Hiroshi Furuta

IPC分类号： H01L25/00

CPC分类号： H03K5/05 ,  H01L2924/0002 ,  H03K3/0375 ,  H03K3/356156 ,  H03K2005/00058 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control. signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.

摘要翻译： 一种半导体集成电路装置，具备包含多个场效应晶体管的功能电路部，模式控制电路，接收第一控制信号，生成用于改变功能电路部的逻辑状态的第二控制信号， 输出控制电路，其接收功能电路部分的输出信号并控制输出信号的输出;以及控制电路，其接收第二控制信号并向输出控制电路产生第三控制信号。 在功能电路部分根据第二控制改变逻辑状态的时间段期间。 信号，输出控制电路根据第三控制信号反转功能电路部分的输出信号。

公开(公告)号：US07276956B2

公开(公告)日：2007-10-02

申请号：US11157832

申请日：2005-06-22

申请人： Hiroshi Furuta ,  Kenjyu Shimogawa

发明人： Hiroshi Furuta ,  Kenjyu Shimogawa

IPC分类号： G05F1/10

CPC分类号： G01K7/01 ,  H01L23/34 ,  H01L2224/48091 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit apparatus according to one embodiment of the invention has an NMOS transistor and a source voltage controller which controls the source voltage of the NMOS transistor according to operation mode. The source voltage controller changes the source voltage according to temperature. Since this integrated circuit apparatus changes the source voltage of the MOSFET based on temperature, it is controlled to have desired leakage current regardless of temperature change.

摘要翻译： 根据本发明的一个实施例的集成电路装置具有NMOS晶体管和源极电压控制器，其根据操作模式控制NMOS晶体管的源极电压。 源电压控制器根据温度改变电源电压。 由于该集成电路装置基于温度改变MOSFET的源极电压，因此无论温度变化如何，均被控制为具有期望的漏电流。