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1.发明授权
公开(公告)号：US5726654A
公开(公告)日：1998-03-10
申请号：US562186
申请日：1995-11-22
申请人： Hiroshi Hatae , Hajime Akimoto
发明人： Hiroshi Hatae , Hajime Akimoto
摘要： An analog to digital converter capable of compensating characteristic unevenness of a signal amplification unit provided at a foregoing part of an analog to digital conversion unit and a signal conversion apparatus using the analog to digital converter are disclosed. An input signal is inputted to an analog to digital conversion unit after being converted from a first physical quantity into a second physical quantity by a signal processing unit. Further, a standard signal is converted from the first physical quantity into the second physical quantity by another or the same processing unit having the same function and is inputted to the analog to digital conversion unit. In the analog to digital conversion unit, analog to digital conversion is performed using the standard signal converted into this second physical quantity.
摘要翻译： 公开了一种模数转换器，其能够补偿在模数转换单元的上述部分提供的信号放大单元的特性不均匀性和使用该模数转换器的信号转换装置。 在由信号处理单元从第一物理量转换为第二物理量之后，将输入信号输入到模数转换单元。 此外，标准信号由具有相同功能的另一个或相同的处理单元从第一物理量转换成第二物理量，并被输入到模数转换单元。 在模数转换单元中，使用转换成该第二物理量的标准信号进行模数转换。
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公开(公告)号：US06433584B1
公开(公告)日：2002-08-13
申请号：US09700925
申请日：2000-11-21
申请人： Hiroshi Hatae
发明人： Hiroshi Hatae
IPC分类号： H03K19175
CPC分类号： H03K19/0016
摘要： The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches which supply power to the logic circuit block, and a switch control circuit which controls the power supply switches. The switch control circuit switch-controls the power supply switches so as to bring a period shorter than the cycle of the clock signal to an on operation period in synchronism with a clock signal. When the logic circuit block is supposed to be activated in synchronism with a clock signal having a frequency lower than a clock signal frequency for defining the maximum operation speed of the logic circuit block, the logic circuit block does not develop a malfunction theoretically if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed. Since the supplying of operating power to the logic circuit block is cut off according to the clock signal frequency except for a period necessary for a circuit operation, leak current that will flow through each turned-off transistor in the meantime, can be significantly reduced.
摘要翻译： 本发明包括与时钟信号同步操作的逻辑电路块，向逻辑电路块供电的电源开关，以及控制电源开关的开关控制电路。 开关控制电路开关控制电源开关，使时钟信号的周期比时钟信号的周期短。 当逻辑电路块被假定与具有低于用于定义逻辑电路块的最大操作速度的时钟信号频率的时钟信号同步地激活时，逻辑电路块在理论上不会产生故障，如果能够 至少仅在由最大操作速度的时钟信号频率定义的时间间隔内对时钟信号的每个周期进行操作。 由于除了电路操作所需的时间之外，根据时钟信号频率将逻辑电路块的工作电源的供给切断，所以可以显着地减少流过每个截止晶体管的泄漏电流。
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公开(公告)号：US06501300B2
公开(公告)日：2002-12-31
申请号：US09900958
申请日：2001-07-10
申请人： Hiroshi Hatae
发明人： Hiroshi Hatae
IPC分类号： H03K1900
CPC分类号： H03K19/0016
摘要： The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches, and a power supply switch control circuit for switch-controlling the power supply switches so as to provide an operation period shorter than the cycle of the clock signal. When the logic circuit block activated in synchronism with a clock signal has a frequency lower than a clock signal frequency, the logic circuit block does not develop a malfunction if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed. Since the supplying of operating power to the logic circuit block is cut off according to the clock signal frequency except for a period necessary for a circuit operation, leak current, that will flow through each turned-off transistor in the meantime, can be significantly reduced.
摘要翻译： 本发明包括与时钟信号同步操作的逻辑电路块，电源开关和用于开关控制电源开关的电源开关控制电路，以便提供比时钟信号的周期短的操作周期 。 当与时钟信号同步激活的逻辑电路块具有低于时钟信号频率的频率时，如果能够对时钟信号的每个周期进行操作，则逻辑电路块至少仅在定义的时间间隔内产生故障 按时钟信号频率的最大运行速度。 由于除电路操作所需的时间外，根据时钟信号频率将逻辑电路块的工作电源的供给切断，所以同时流过各截止晶体管的漏电流可以显着降低 。
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公开(公告)号：US06889274B2
公开(公告)日：2005-05-03
申请号：US09870630
申请日：2001-06-01
申请人： Hiromi Watanabe , Takashi Nakamoto , Hiroshi Hatae , Junko Haruta , Masaru Hase , Kenichi Iwata , Hiroshi Yamada , Yutaka Okada
发明人： Hiromi Watanabe , Takashi Nakamoto , Hiroshi Hatae , Junko Haruta , Masaru Hase , Kenichi Iwata , Hiroshi Yamada , Yutaka Okada
CPC分类号： H04N19/423 , G06F3/14 , G09G5/363 , H04N19/61
摘要： A signal processing circuit having a data input-output (I/O) circuit, a microprocessor, a dedicated processing circuit, a local memory, and a memory access control circuit interconnected over a bus. The system bus connects to the data I/O circuit, microprocessor, dedicated processing circuit, and memory access control circuit. A local memory bus connects to the local memory. First, second, and third connection circuits connect between the system bus and local memory bus, between a first local bus in the dedicated processing circuit and the local memory bus, and between a second local bus in the data I/O circuit and the local memory bus. The memory access control circuit controls the first, second, and third connection circuits according to priorities assigned for the connection circuits and determines which of the second local bus, first local bus, and system bus will be connected to the local memory bus.
摘要翻译： 具有通过总线互连的数据输入输出（I / O）电路，微处理器，专用处理电路，本地存储器和存储器访问控制电路的信号处理电路。 系统总线连接到数据I / O电路，微处理器，专用处理电路和存储器访问控制电路。 本地存储器总线连接到本地存储器。 第一，第二和第三连接电路连接在系统总线和本地存储器总线之间，专用处理电路中的第一本地总线与本地存储器总线之间，以及数据I / O电路中的第二局部总线与本地存储器总线之间 内存总线 存储器访问控制电路根据分配给连接电路的优先级来控制第一，第二和第三连接电路，并确定第二本地总线，第一局部总线和系统总线中的哪一个将连接到本地存储器总线。
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公开(公告)号：US06496539B2
公开(公告)日：2002-12-17
申请号：US10033928
申请日：2002-01-03
申请人： Hiromi Watanabe , Kenichi Iwata , Hiroshi Hatae
发明人： Hiromi Watanabe , Kenichi Iwata , Hiroshi Hatae
IPC分类号： H04N736
CPC分类号： H04N19/523 , H04N19/433
摘要： There is disclosed a method and apparatus for detecting motion by a video encoder. The method starts with dividing a target block whose motion is to be detected into blocks at different pixel positions. A reference image block is extracted from a reference image. The degrees of similarity of the blocks to the reference image block are simultaneously calculated by a calculating unit. A block having the highest degree of similarity is determined, based on their degrees of similarity. A vector corresponding to the determined block is taken as a motion vector representing the block.
摘要翻译： 公开了一种用于检测视频编码器的运动的方法和装置。 该方法开始于将要检测的运动的目标块划分为不同像素位置的块。 从参考图像中提取参考图像块。 通过计算单元同时计算块与参考图像块的相似度。 基于相似度确定具有最高相似度的块。 将与确定的块相对应的向量作为表示块的运动矢量。
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公开(公告)号：US06370195B1
公开(公告)日：2002-04-09
申请号：US09289678
申请日：1999-04-12
申请人： Hiromi Watanabe , Kenichi Iwata , Hiroshi Hatae
发明人： Hiromi Watanabe , Kenichi Iwata , Hiroshi Hatae
IPC分类号： H04N736
CPC分类号： H04N19/523 , H04N19/433
摘要： There is disclosed a method and apparatus for detecting motion by a video encoder. The method starts with dividing a target block whose motion is to be detected into blocks at different pixel positions. A reference image block is extracted from a reference image. The degrees of similarity of the blocks to the reference image block are simultaneously calculated by a calculating unit. A block having the highest degree of similarity is determined, based on their degrees of similarity. A vector corresponding to the determined block is taken as a motion vector representing the block.
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