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公开(公告)号：US4897637A
公开(公告)日：1990-01-30
申请号：US33466
申请日：1987-04-02
CPC分类号： G09G5/222
摘要： A display controller including a first ROM, a second ROM, a RAM, and an output circuit. The first ROM stores fixed data to be displayed on a fixed data area of a display screen. The RAM stores variable data to be displayed on a variable data area of the display screen and receives controlling addresses from the first ROM. The second ROM, under control of data from a preselected one of the first ROM or the RAM, outputs the display pattern data to be displayed on the display device. The output circuit latches the display pattern data and sends it to the display device at a predetermined timing.
摘要翻译： 一种显示控制器，包括第一ROM，第二ROM，RAM和输出电路。 第一个ROM存储要显示在显示屏的固定数据区上的固定数据。 RAM存储要显示在显示屏的可变数据区上的变量数据，并接收来自第一ROM的控制地址。 第二ROM在来自第一ROM或RAM中的预先选择的数据的数据的控制下，输出要显示在显示装置上的显示图案数据。 输出电路锁存显示图案数据，并以预定的定时将其发送到显示装置。
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公开(公告)号：US5266939A
公开(公告)日：1993-11-30
申请号：US803902
申请日：1991-12-09
摘要： A ROM part (24) of a charactor ROM (21) stores a plurality of font data. A display data RAM (9) simultaneously supplies a plurality of address signals to the charactor ROM (21) which is provided with a plurality of address decoders (25, 26). Respective address signals are decoded by the corresponding address decoders (25, 26), so that the font data corresponding to the address signals are read on the common bit lines (BL.sub.1 -BL.sub.l). Thus, the font data as read are synthesized on the common bit lines (BL.sub.1 -BL.sub.l) as a logical sum.
摘要翻译： 字符串ROM（21）的ROM部分（24）存储多个字体数据。 显示数据RAM（9）同时向设置有多个地址解码器（25,26）的字符串ROM（21）提供多个地址信号。 相应的地址信号由相应的地址解码器（25,26）解码，使得在公共位线（BL1-BL1）上读取对应于地址信号的字体数据。 因此，读出的字体数据在公共位线（BL1-BL1）上合成为逻辑和。
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公开(公告)号：US4914428A
公开(公告)日：1990-04-03
申请号：US55129
申请日：1987-05-28
IPC分类号： G08C19/28
CPC分类号： G08C19/28
摘要： A digital remote control apparatus for transmitting digital instruction signals to a controllable apparatus includes a transmitter for transmitting a coded digital instruction signal composed of a sequence of synchronization pulses having a predetermined period and data pulses each inserted between successive synchronization pulses at predetermined positions therein dependent upon whether the data pulses represents a "0" bit or a "1" bit. The receiving apparatus distinguishes between "0" and "1" bits by detecting the length of an interval between the leading edge of a synchronization pulse and the leading edge of an adjacent data pulse and determines the existence of noise if more than one data pulse is detected between successive synchronzation pulses. In this way, information decoding is facilitated by enabling the length of each data word to be constant, regardless of the number of ones and zeroes in the word, and also facilitates the detection of communication transmission error by detecting the presence of more than one data pulse between successive synchronization pulses of a constant period as being noise.
摘要翻译： 一种用于将数字指令信号发送到可控制装置的数字遥控装置包括发射机，用于发送编码的数字指令信号，该编码数字指令信号由具有预定周期的同步脉冲序列组成，数据脉冲各自插入在依赖于 数据脉冲是否表示“0”位或“1”位。 接收装置通过检测同步脉冲的前沿与相邻数据脉冲的前沿之间的间隔的长度来区分“0”和“1”比特，并且如果多于一个的数据脉冲是 在连续的同步脉冲之间检测。 以这种方式，通过使得每个数据字的长度能够保持恒定，而不管单词中的一个和多个的数目如何，便于信息解码，并且还通过检测多于一个数据的存在而有助于检测通信传输错误 在一个恒定周期的连续同步脉冲之间的脉冲作为噪声。
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公开(公告)号：US4833467A
公开(公告)日：1989-05-23
申请号：US19178
申请日：1987-02-26
申请人： Hiroshi Kobayashi , Shinji Suda , Katsunobu Hongo
发明人： Hiroshi Kobayashi , Shinji Suda , Katsunobu Hongo
CPC分类号： G08C19/28
摘要： In a digital data transmission system, a transmitting device converts the data to be transmitted into a series of bits, in the form of data pulses. Each data pulse is positioned between successive synchronous pulses having a fixed time period, and each bit is represented by the time length between a data pulse and a preceding synchronous pulse or a succeeding synchronous pulse. The transmitting device transmits the series of the data pulses and the synchronous pulses. A receiving device receives the series of the data pulses and the synchronous pulses and decodes the same to read the data.
摘要翻译： 在数字数据传输系统中，发送装置以数据脉冲的形式将要发送的数据转换成一系列位。 每个数据脉冲位于具有固定时间段的连续同步脉冲之间，并且每个位由数据脉冲和先前同步脉冲或后续同步脉冲之间的时间长度表示。 发送装置发送一系列数据脉冲和同步脉冲。 接收装置接收一系列数据脉冲和同步脉冲，并对其进行解码以读取数据。
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5.发明授权Complementary circuit device returnable to normal operation from latch-up phenomenon 失效补充电路恢复正常操作的补充电路设备
公开(公告)号：US5140177A
公开(公告)日：1992-08-18
申请号：US442754
申请日：1989-11-29
IPC分类号： H03K17/082 , H03K17/22
CPC分类号： H03K17/223 , H03K17/0822
摘要： A complementary circuit device which cancels a latch-up phenomenon to return to normal operation includes a complementary circuit, a latch-up detection circuit and a reset circuit. The complementary circuit, which is normally started from a prescribed logic state in response to an initial power application of power to the circuit, is susceptible to erroneous restart when the same is resupplied with power immediately after occurrence of a latch-up phenomenon. The latch-up detection circuit detects a latch-up phenomenon occurring in the complementary circuit. The reset circuit resets the complementary circuit to the prescribed logic state in response to an output from the latch-up detection circuit. The complementary circuit is reset again to the prescribed state in a manner similar to the case of initial application of power. The invention facilitates a normal return to operation of a complementary circuit upon cancellation of the latch-up phenomenon.
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公开(公告)号：US4931790A
公开(公告)日：1990-06-05
申请号：US154451
申请日：1988-02-08
申请人： Hiroshi Kobayashi , Shinji Suda
发明人： Hiroshi Kobayashi , Shinji Suda
摘要： A digital remote control method in which interference among different devices is eliminated by the use of a custom code and an instruction code. In accordance with the invention, a transmission code is generated composed of an instruction code and a custom code, with the custom code and instruction code differing in the number of bits contained in each. The custom code is transmitted prior to the instruction code with an interval therebetween longer than the intervals between adjacent pulses, which intervals define data "0" and "1".
摘要翻译： 通过使用定制代码和指令代码来消除不同设备之间的干扰的数字遥控方法。 根据本发明，生成由指令代码和自定义代码组成的传输代码，其中定制代码和指令代码在每个中包含的位数不同。 定制代码在指令代码之前以间隔长于相邻脉冲之间的间隔发送，该间隔定义数据“0”和“1”。
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公开(公告)号：US4814741A
公开(公告)日：1989-03-21
申请号：US43608
申请日：1987-04-28
CPC分类号： G08C19/28
摘要： A digital remote control device for use in a transmitter capable of transmitting an end code following each transmission code, which includes a counting circuit for counting the number of transmission operations performed by pressing a key or keys on the transmitter; and an end pulse changing circuit for changing a configuration of the end code such that the configuration corresponds to a count value counted by the counting circuit.
摘要翻译： 一种数字遥控装置，用于能够发送每个传输码之后的结束码的发射机，该数字遥控装置包括：计数电路，用于对通过按下发射机上的一个或多个键执行的传输操作的数量进行计数; 以及结束脉冲改变电路，用于改变结束码的配置，使得该配置对应于由计数电路计数的计数值。
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8.发明授权公开(公告)号：US12020462B2
公开(公告)日：2024-06-25
申请号：US17391308
申请日：2021-08-02
申请人： Hiroshi Kobayashi , Takahiro Watanabe , Ryo Taneda
发明人： Hiroshi Kobayashi , Takahiro Watanabe , Ryo Taneda
IPC分类号： G06K9/00 , G06V10/22 , G06V30/412 , G06V30/416 , G06V30/10
CPC分类号： G06V10/225 , G06V30/412 , G06V30/416 , G06V30/10
摘要： An information processing apparatus includes a processor configured to perform operations including extracting information indicative of an issuer of a form from form image data, and obtaining fixed information corresponding to the information indicative of the issuer of the form by referring to a storage storing the fixed information associated with the issuer of the form, and outputting, to a terminal apparatus, screen data including the information indicative of the issuer of the form and the obtained fixed information.
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公开(公告)号：US11113559B2
公开(公告)日：2021-09-07
申请号：US16512604
申请日：2019-07-16
IPC分类号： G06K9/46
摘要： An information processing apparatus includes processing circuitry that acquires an electronic file containing first text data, and determines, based on the acquired electronic file, whether to use the first text data or second text data to perform a process. The second text data is generated through character recognition performed on an image contained in the acquired electronic file.
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公开(公告)号：US10541817B2
公开(公告)日：2020-01-21
申请号：US15447334
申请日：2017-03-02
申请人： Hitoshi Namiki , Hiroshi Kobayashi , Ryouji Yamamoto , Eiichiro Yoshida , Masuyoshi Yachida , Yuki Takaya
发明人： Hitoshi Namiki , Hiroshi Kobayashi , Ryouji Yamamoto , Eiichiro Yoshida , Masuyoshi Yachida , Yuki Takaya
摘要： A data generation apparatus includes a processor that executes a process including obtaining target data sequentially from time-series data, the target data including n (n being an integer greater than or equal to 2) data items in a predetermined section of the time-series data, calculating parameter information satisfying a (k−1) order polynomial based on the target data, the (k−1) order polynomial including k random values, k being an integer greater than or equal to 1 and less than n, associating the target data to the parameter information, outputting the target data and the parameter information associated to the target data, attaching a signature to secret information based on a secret distributed protocol. The secret information is calculable by using k pairs of data including the target data and the parameter information associated to the target data, and outputting the secret information attached with the signature.
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