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公开(公告)号：US20130015518A1
公开(公告)日：2013-01-17
申请号：US13353818
申请日：2012-01-19
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/764 , H01L27/11524 , H01L29/40114 , H01L29/42336 , H01L29/66825
摘要： In general, according to one embodiment, a semiconductor memory device includes active areas extending in a first direction, tunnel films provided on the active areas, floating gate electrodes provided on the tunnel films, an interelectrode insulating film provided on the floating gate electrodes and extending in a second direction, a control gate electrode provided on the interelectrode insulating film and extending in the second direction, a lower insulating portion provided between the active areas, between the tunnel films, and between the floating gate electrodes adjacent in the second direction, and an upper insulating portion provided between the lower insulating portion and the interelectrode insulating film. The lower insulating portion includes a void. Relative dielectric constant of the upper insulating portion is higher than that of the lower insulating portion. Relative dielectric constant of the interelectrode insulating film is higher than that of the upper insulating portion.
摘要翻译： 通常，根据一个实施例，半导体存储器件包括在第一方向上延伸的有源区域，设置在有源区域上的隧道膜，设置在隧道膜上的浮置栅极电极，设置在浮动栅电极上并延伸的电极间绝缘膜 在第二方向上，设置在电极间绝缘膜上并沿第二方向延伸的控制栅电极，设置在有源区之间，隧道膜之间以及在第二方向相邻的浮栅之间的下绝缘部分，以及 设置在下绝缘部和电极间绝缘膜之间的上绝缘部。 下绝缘部分包括空隙。 上绝缘部分的相对介电常数高于下绝缘部分的相对介电常数。 电极间绝缘膜的相对介电常数高于上绝缘部分。
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2.发明申请NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD OF WRITING THE SAME, AND SEMICONDUCTOR DEVICE 审中-公开非挥发性半导体存储器件，其写入方法和半导体器件公开(公告)号：US20120106246A1
公开(公告)日：2012-05-03
申请号：US13052180
申请日：2011-03-21
申请人： Hidefumi NAWATA
发明人： Hidefumi NAWATA
CPC分类号： G11C11/5642 , G11C16/10 , G11C16/3418
摘要： A control circuit is configured to be able to perform a rough write process, a foggy write process, and a fine write process. The rough write process moves, for a memory cell to be provided with a plurality of second threshold voltage distributions, a first threshold voltage distribution in the positive direction to generate a third threshold voltage distribution. The foggy write process does not move, for a memory cell finally to be provided with first data, the third threshold voltage distribution, and moves, for a memory cell finally to be provided with second data different from the first data, the first threshold voltage distribution or the third threshold voltage distribution in the positive direction to generate a plurality of fourth threshold voltage distributions. The fine write process moves the fourth threshold voltage distributions in the positive direction to generate the second threshold voltage distributions.
摘要翻译： 控制电路被配置为能够执行粗写入处理，雾写入处理和精细写入处理。 对于要提供多个第二阈值电压分布的存储器单元，粗加工过程移动在正方向上的第一阈值电压分布以产生第三阈值电压分布。 雾状写入过程不会移动，为了使存储器单元最终被提供有第一数据，第三阈值电压分布和移动，对于最终提供有与第一数据不同的第二数据的存储单元，第一阈值电压 分布或第三阈值电压分布，以产生多个第四阈值电压分布。 精细写入处理将第四阈值电压分布沿正方向移动以产生第二阈值电压分布。
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3.发明申请公开(公告)号：US20130088924A1
公开(公告)日：2013-04-11
申请号：US13423708
申请日：2012-03-19
申请人： Hidefumi NAWATA
发明人： Hidefumi NAWATA
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3436
摘要： A bit line is electrically connected to one end of a current path of a memory cell. A word line is commonly connected to the memory cells arranged in a direction intersecting the bit line. A control circuit executes a write operation for applying a write voltage to the word line so shift a threshold voltage of the memory cell to be data written that the threshold voltage of the memory cell to be data written reaches a certain threshold voltage. During the write operation, the control circuit, while applying a gradually rising write voltage to the word line, gradually changes a voltage applied to the bit line based on a relationship between the threshold voltage of the memory cell to be written and a number of times of the write voltage applications.
摘要翻译： 位线电连接到存储器单元的当前路径的一端。 字线通常连接到沿与位线相交的方向排列的存储单元。 控制电路执行用于向字线施加写入电压的写入操作，从而将要写入的数据的存储器单元的阈值电压移位为要写入数据的存储器单元的阈值电压达到一定的阈值电压。 在写入操作期间，控制电路在向字线施加逐渐增加的写入电压的同时，基于要写入的存储器单元的阈值电压与次数之间的关系逐渐改变施加到位线的电压 的写电压应用。
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公开(公告)号：US20120250419A1
公开(公告)日：2012-10-04
申请号：US13232259
申请日：2011-09-14
申请人： Hidefumi NAWATA , Kiyomi Naruke
发明人： Hidefumi NAWATA , Kiyomi Naruke
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3427
摘要： In one embodiment, method of controlling a semiconductor nonvolatile memory device includes determining data written to an adjacent memory cell which is adjacent to a selection memory cell in memory cells configured as a matrix, the selection memory being selected by a program operation for writing the data to the selection memory, and writing the data to the selection memory with controlling an amount of charges injected into the selection memory based on a result of determining the data.
摘要翻译： 在一个实施例中，控制半导体非易失性存储器件的方法包括确定写入与配置为矩阵的存储器单元中的与选择存储器单元相邻的相邻存储器单元的数据，所述选择存储器通过用于写入数据的程序操作来选择 到选择存储器，并且基于确定数据的结果，控制注入到选择存储器中的电荷量，将数据写入选择存储器。
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公开(公告)号：US20120236637A1
公开(公告)日：2012-09-20
申请号：US13223891
申请日：2011-09-01
申请人： Hidefumi NAWATA
发明人： Hidefumi NAWATA
IPC分类号： G11C16/28
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/28 , G11C16/3404
摘要： A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells are connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control circuit configured to execute a write operation by applying a write voltage to the word line. The control circuit is configured to execute a correction write operation accompanied by the write operation and executed on a selected memory cell, when a threshold voltage of data written in a reference memory cell is an erase level, the reference memory cell being the memory cell adjacent to the selected memory cell and in which the data is written after the write operation on the selected memory cell.
摘要翻译： 根据一个实施例的非易失性半导体存储装置包括存储单元阵列，其具有多个存储单元串联连接的NAND单元单元，多个存储单元中的每一个的控制栅极连接到字线 以及控制电路，被配置为通过向字线施加写入电压来执行写入操作。 控制电路被配置为当写入参考存储单元的数据的阈值电压为擦除电平时，执行伴随着写入操作并在所选存储单元上执行的校正写入操作，该参考存储器单元是相邻的存储器单元 到所选择的存储单元，并且在对所选存储单元进行写操作之后写入数据。
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公开(公告)号：US20130070532A1
公开(公告)日：2013-03-21
申请号：US13418881
申请日：2012-03-13
申请人： Hidefumi NAWATA
发明人： Hidefumi NAWATA
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/10
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a control unit configured to perform a control of repeating a program operation, and a step-up operation, the program operation being an operation of applying a program pulse voltage to a selected memory cell and applying an intermediate voltage less than the program pulse voltage to first and second non-selected memory cells adjacent to the selected memory cell, and the step-up operation being an operation of increasing the program pulse voltage by a first step-up value. For a first period, the control unit maintains the intermediate voltage to be a constant value. For a second period, the control unit controls the step-up operation such that the intermediate voltage is increased by a second step-up value, and determines the first step-up value on the basis of the second step-up value.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：控制单元，被配置为执行重复编程操作的控制;以及升压操作，所述编程操作是将编程脉冲电压施加到所选择的存储单元并施加 对与所选择的存储单元相邻的第一和第二非选择存储单元的编程脉冲电压小于编程脉冲电压的中间电压，升压操作是将编程脉冲电压增加第一升压值的操作。 在第一时段中，控制单元将中间电压保持为恒定值。 在第二时段中，控制单元控制升压操作使得中间电压增加第二升压值，并且基于第二升压值确定第一升压值。
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公开(公告)号：US20120236636A1
公开(公告)日：2012-09-20
申请号：US13223685
申请日：2011-09-01
申请人： Hidefumi NAWATA
发明人： Hidefumi NAWATA
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/28 , G11C16/3427
摘要： A non-volatile semiconductor storage device according to an embodiment includes a memory cell array and a control circuit configured to execute a read operation. The control circuit refers to data of a reference memory cell which is adjacent to a selected memory cell and in which data is written after a data write operation on the selected memory cell. The control circuit applies a first read pass voltage to a non-selected word line adjacent to the selected word line, when the data of the reference memory cell is data causing the shift of the threshold voltage of the selected memory cell. The control circuit applies a second read pass voltage lower than the first read pass voltage to the non-selected word line, when the data of the reference memory cell is data not causing the shift of the threshold voltage of the selected memory cell.
摘要翻译： 根据实施例的非易失性半导体存储装置包括被配置为执行读取操作的存储单元阵列和控制电路。 控制电路是指与所选择的存储单元相邻的参考存储单元的数据，并且在对选择的存储单元进行数据写入操作之后写入数据。 当参考存储单元的数据是导致所选存储单元的阈值电压偏移的数据时，控制电路将第一读通道电压施加到与所选字线相邻的未选字线。 当参考存储单元的数据是不导致所选存储单元的阈值电压偏移的数据时，控制电路将低于第一读通过电压的第二读通过电压施加到未选择的字线。
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公开(公告)号：US20110239096A1
公开(公告)日：2011-09-29
申请号：US12884882
申请日：2010-09-17
申请人： Hidefumi NAWATA
发明人： Hidefumi NAWATA
CPC分类号： G11C16/10 , G06F11/1068
摘要： A memory element array includes plural memory elements capable of storing M-value data (M is a natural number not smaller than 2). Among first to M-th data, the first data gives a largest physical impact on memory elements.A data processing unit can execute a data process on an aggregate of program data stored in a data storing unit. It is determined that which of the first to the M-th data is least existing data, the number of pieces of which is the smallest in the aggregate of the program data. When the least existing data is other than the first data, the least existing data in the aggregate of program data is replaced with the first data, and the first data with the least existing data.When the least existing data is the first data, the aggregate of program data is maintained without any data replacement.
摘要翻译： 存储元件阵列包括能够存储M值数据的多个存储器元件（M是不小于2的自然数）。 在第一到第M个数据中，第一个数据给存储器元件带来最大的物理影响。 数据处理单元可以对存储在数据存储单元中的程序数据的集合执行数据处理。 确定第一至第M数据中的哪一个是最少存在的数据，其数量是节目数据的总和中最小的数量。 当最不存在的数据不是第一数据时，程序数据的汇总中的最少现有数据被替换为第一数据，并且具有最小存在数据的第一数据。 当最小现有数据是第一个数据时，维护程序数据的汇总而无需任何数据替换。
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公开(公告)号：US20120243324A1
公开(公告)日：2012-09-27
申请号：US13223569
申请日：2011-09-01
申请人： Hidefumi NAWATA
发明人： Hidefumi NAWATA
CPC分类号： G11C16/06 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control circuit configured to execute a write operation by applying a certain write voltage to the word line multiple times to set a threshold voltage of the memory cell to a value corresponding to data. The control circuit is configured to control the write voltage such that the write voltage is increased by a first step-up voltage when the write voltage is repeatedly applied in a first period after the write operation starts, and the write voltage is increased by a second step-up voltage lower than the first step-up voltage in a second period after the first period.
摘要翻译： 根据一个实施例的非易失性半导体存储装置包括存储单元阵列，其具有串联连接的多个存储单元的NAND单元单元，多个存储单元中的每一个的控制栅极连接到字线， 以及控制电路，被配置为通过对字线施加一定的写入电压来执行写入操作多次以将存储器单元的阈值电压设置为与数据对应的值。 控制电路被配置为控制写入电压，使得当在写入操作开始之后的第一周期中重复施加写入电压时，写入电压增加第一升压电压，并且写入电压增加第二 在第一时段之后的第二周期中升压电压低于第一升压电压。
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公开(公告)号：US20120020160A1
公开(公告)日：2012-01-26
申请号：US13020401
申请日：2011-02-03
申请人： Hidefumi NAWATA
发明人： Hidefumi NAWATA
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/3418
摘要： A control circuit is configured to execute a writing operation for giving a second threshold voltage distribution to a plurality of memory cells formed along one word line. In the writing operation, the control circuit performs a writing operation by executing a voltage applying operation in memory cells to be given the second threshold voltage distribution. While the control circuit executes a voltage applying operation in memory cells to be maintained in an erased state, thereby moving a first threshold voltage distribution to a positive direction to obtain a third threshold voltage distribution representing the erased state.
摘要翻译： 控制电路被配置为执行用于给沿着一个字线形成的多个存储单元提供第二阈值电压分布的写入操作。 在写入操作中，控制电路通过在存储单元中执行施加电压来执行写入操作以被赋予第二阈值电压分布。 当控制电路在保持在擦除状态的存储单元中执行电压施加操作时，由此将第一阈值电压分布移动到正方向以获得表示擦除状态的第三阈值电压分布。
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