公开(公告)号：US20120281985A1

公开(公告)日：2012-11-08

申请号：US13463136

申请日：2012-05-03

申请人： Hiroyuki HONMA ,  Masahiro Shioda ,  Toru Katagiri

发明人： Hiroyuki HONMA ,  Masahiro Shioda ,  Toru Katagiri

IPC分类号： H04J14/08

CPC分类号： H04J3/1652 ,  H04J2203/0089

摘要： A transmitting apparatus includes a frame dividing circuit that maps frame data of each of a plurality of frames whose period is different from each other into one or a plurality of internal frames having a fixed frame period and a fixed transmission rate, based on a predetermined internal clock; a cross-connect circuit that cross-connects the frame data of each in a time division multiplexing system based on the internal clock in units of the internal frames; and a frame combining circuit that demaps, into any of the plurality of frames, or multiplexes, data of one or a plurality of internal frames cross-connected by the cross-connect circuit.

摘要翻译： 发送装置包括帧分割电路，其基于预定的内部将帧周期彼此不同的多个帧的帧数据映射到具有固定帧周期和固定传输速率的一个或多个内部帧 时钟; 交叉连接电路，以内部时钟为单位，以时分复用系统中的各帧的帧数据交叉连接; 以及帧合成电路，其将多个帧中的任一个解映射或多路复用由交叉连接电路交叉连接的一个或多个内部帧的数据。

公开(公告)号：US08824507B2

公开(公告)日：2014-09-02

申请号：US13463136

申请日：2012-05-03

申请人： Hiroyuki Honma ,  Masahiro Shioda ,  Toru Katagiri

发明人： Hiroyuki Honma ,  Masahiro Shioda ,  Toru Katagiri

IPC分类号： H04J3/24 ,  H04J3/16

CPC分类号： H04J3/1652 ,  H04J2203/0089

摘要： A transmitting apparatus includes a frame dividing circuit that maps frame data of each of a plurality of frames whose period is different from each other into one or a plurality of internal frames having a fixed frame period and a fixed transmission rate, based on a predetermined internal clock; a cross-connect circuit that cross-connects the frame data of each in a time division multiplexing system based on the internal clock in units of the internal frames; and a frame combining circuit that demaps, into any of the plurality of frames, or multiplexes, data of one or a plurality of internal frames cross-connected by the cross-connect circuit.

摘要翻译： 发送装置包括帧分割电路，其基于预定的内部将帧周期彼此不同的多个帧的帧数据映射到具有固定帧周期和固定传输速率的一个或多个内部帧 时钟; 交叉连接电路，以内部时钟为单位，以时分复用系统中的各帧的帧数据交叉连接; 以及帧合成电路，其将多个帧中的任一个解映射或多路复用由交叉连接电路交叉连接的一个或多个内部帧的数据。

公开(公告)号：US20130058643A1

公开(公告)日：2013-03-07

申请号：US13665146

申请日：2012-10-31

申请人： Hiroyuki HONMA ,  Toru Katagiri ,  Hiromichi Makishima ,  Masahiro Shioda ,  Hiroyuki Kitajima ,  Ichiro Yokokura

发明人： Hiroyuki HONMA ,  Toru Katagiri ,  Hiromichi Makishima ,  Masahiro Shioda ,  Hiroyuki Kitajima ,  Ichiro Yokokura

IPC分类号： H04B10/08

CPC分类号： H04J3/1652 ,  H04J2203/0058 ,  H04L43/0876

摘要： A data amount derivation apparatus includes: a first calculator configured to derive, for one series of parallelized mapping signals, amount of data in each frame period for a frame into which the parallelized mapping signals are mapped; and a second calculator configured to sum up amounts of data in N frame periods, where N is an integer, and to derive the resulting summation value as the amount of data to be mapped into the frame, each of the amounts of data in each of the frame periods being derived by the first calculator.

摘要翻译： 数据量导出装置包括：第一计算器，被配置为针对一系列并行映射信号，对并行映射信号映射到的帧的每个帧周期中的数据量; 以及第二计算器，被配置为对N个帧周期内的数据量进行相加，其中N是整数，并且导出所得到的求和值作为要映射到该帧中的数据量，每个数据量 帧周期由第一计算器导出。

公开(公告)号：US08687655B2

公开(公告)日：2014-04-01

申请号：US13400827

申请日：2012-02-21

申请人： Toru Katagiri ,  Masahiro Shioda

发明人： Toru Katagiri ,  Masahiro Shioda

IPC分类号： H04J3/24

CPC分类号： H04J3/1652

摘要： A signal demultiplexer includes a conversion unit that converts a format of a high speed signal transfer frame output from a terminating unit into a format of a converted frame; a parallelization unit that parallelizes the converted frame and outputs a predetermined number of data columns; and a separating unit that separates plural low speed signal transfer frames from the predetermined number of the data columns. The conversion unit converts the format of the high speed signal transfer frame into the format of the converted frame by delaying a signal storing area using first and second overhead areas, to include an “i” th tributary slot among the predetermined number of the tributary slots assigned to the signal storing area into an arbitrary “i” th data column among the predetermined number of the data columns, and to align front positions of the predetermined number of the data columns.

摘要翻译： 信号解复用器包括转换单元，其将从终端单元输出的高速信号传送帧的格式转换为转换帧的格式; 并行化单元，其并行化所转换的帧并输出预定数量的数据列; 以及分离单元，其从预定数量的数据列分离多个低速信号传送帧。 转换单元通过使用第一和第二开销区域延迟信号存储区域来将高速信号传送帧的格式转换为转换帧的格式，以在预定数量的辅助时隙中包括“第i个”支路时隙 分配给信号存储区域到预定数量的数据列中的任意“第i”个数据列，并且对准预定数量的数据列的前端位置。

公开(公告)号：US08675684B2

公开(公告)日：2014-03-18

申请号：US12719277

申请日：2010-03-08

申请人： Toru Katagiri ,  Masahiro Shioda

发明人： Toru Katagiri ,  Masahiro Shioda

IPC分类号： H04J3/24

CPC分类号： H04J3/076 ,  H04J3/1652 ,  H04J3/1664

摘要： A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.

摘要翻译： 以比客户端信号更高的比特率的光数据传输单元帧中容纳客户端信号的帧生成装置包括解串器，多个通用映射程序电路和串行器。 解串器将客户端信号反序列化为并行信号，对应于在光学数据传送单元帧中使用的支路数量的并行信号的数量。 多个通用映射程序电路基于客户端信号与光学数据传送单元帧之间的比特率的差异将数据和填充物插入到光学数据传送单元帧的帧容纳部分中。 串行器串行化从多个通用映射程序电路输出的并行信号。

公开(公告)号：US20100226648A1

公开(公告)日：2010-09-09

申请号：US12719277

申请日：2010-03-08

申请人： Toru Katagiri ,  Masahiro Shioda

发明人： Toru Katagiri ,  Masahiro Shioda

IPC分类号： H04J14/00 ,  H04B10/00

CPC分类号： H04J3/076 ,  H04J3/1652 ,  H04J3/1664

摘要： A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.

摘要翻译： 以比客户端信号更高的比特率的光数据传输单元帧中容纳客户端信号的帧生成装置包括解串器，多个通用映射程序电路和串行器。 解串器将客户端信号反序列化为并行信号，对应于在光学数据传送单元帧中使用的支路数量的并行信号的数量。 多个通用映射程序电路基于客户端信号与光学数据传送单元帧之间的比特率的差异将数据和填充物插入到光学数据传送单元帧的帧容纳部分中。 串行器串行化从多个通用映射程序电路输出的并行信号。

公开(公告)号：US08571073B2

公开(公告)日：2013-10-29

申请号：US13365819

申请日：2012-02-03

申请人： Toshiaki Ohkubo ,  Toru Katagiri ,  Hiroyuki Honma ,  Hiromichi Makishima ,  Hiroyuki Kitajima

发明人： Toshiaki Ohkubo ,  Toru Katagiri ,  Hiroyuki Honma ,  Hiromichi Makishima ,  Hiroyuki Kitajima

IPC分类号： H04J3/02

CPC分类号： H04J3/1652

摘要： An apparatus for mapping multiple lower-speed signal transmission frames to a higher-speed signal transmission frame. The apparatus includes buffers configured to buffer the lower-speed signal transmission frames, determination units configured to determine frequency justification information for the lower-speed signal transmission frames, a barrel shifter configured to receive signals output from the buffers, and a controller configured to control the barrel shifter to map the lower-speed signal transmission frames to the higher-speed signal transmission frame based on external settings for the respective lower-speed signal transmission frames and the frequency justification information determined by the determination units. When the minimum unit of the lower-speed signal transmission frames is a channel, the number of the buffers and the number of the determination units correspond to the maximum number of channels that can be multiplexed in the higher-speed signal transmission frame.

摘要翻译： 一种用于将多个低速信号传输帧映射到更高速度的信号传输帧的装置。 该装置包括被配置为缓冲低速信号传输帧的缓冲器，被配置为确定低速信号传输帧的频率调整信息的确定单元，被配置为接收从缓冲器输出的信号的桶形移位器，以及被配置为控制 桶形移位器基于各个低速信号传输帧的外部设置和由确定单元确定的频率对齐信息将低速信号传输帧映射到较高速度的信号传输帧。 当低速信号传输帧的最小单位是信道时，缓冲器的数量和确定单元的数量对应于在高速信号传输帧中可以多路复用的最大信道数。

公开(公告)号：US20110229133A1

公开(公告)日：2011-09-22

申请号：US13047083

申请日：2011-03-14

申请人： Toru Katagiri ,  Hiroyuki Honma

发明人： Toru Katagiri ,  Hiroyuki Honma

IPC分类号： H04J14/00

CPC分类号： H04J3/07 ,  H04J3/0685 ,  H04J3/1652

摘要： A transmission apparatus stores frame data of a first frame in a second frame having a bit rate different from that of the first frame through regulation of the amount of stuffs to be stored in the second frame. The transmission apparatus includes: a storage unit storing the first-frame frame data; a first control unit controlling a timing of writing the first-frame frame data in the storage unit based on first stuff information indicating the amount of stuffs contained in the first frame; an arithmetic and logic unit obtaining second stuff information indicating the amount of stuffs to be contained in the second frame based on a bit rate ratio between the first frame and the second frame; and a second control unit controlling a timing of reading out the first-frame frame data stored in the storage unit based on the second stuff information.

摘要翻译： 发送装置通过调整要存储在第二帧中的填充量来存储具有与第一帧不同的比特率的第二帧中的第一帧的帧数据。 发送装置包括：存储单元，存储第一帧帧数据; 第一控制单元，基于表示第一帧中包含的填充量的第一填充信息，控制将第一帧帧数据写入存储单元的定时; 算术和逻辑单元，基于第一帧和第二帧之间的比特率，获得指示要包含在第二帧中的填充量的第二填充信息; 以及第二控制单元，其基于第二填充信息控制读出存储在存储单元中的第一帧帧数据的定时。

公开(公告)号：US08665738B2

公开(公告)日：2014-03-04

申请号：US13047083

申请日：2011-03-14

申请人： Toru Katagiri ,  Hiroyuki Honma

发明人： Toru Katagiri ,  Hiroyuki Honma

IPC分类号： H04L12/26

CPC分类号： H04J3/07 ,  H04J3/0685 ,  H04J3/1652

摘要： A transmission apparatus stores frame data of a first frame in a second frame having a bit rate different from that of the first frame through regulation of the amount of stuffs to be stored in the second frame. The transmission apparatus includes: a storage unit storing the first-frame frame data; a first control unit controlling a timing of writing the first-frame frame data in the storage unit based on first stuff information indicating the amount of stuffs contained in the first frame; an arithmetic and logic unit obtaining second stuff information indicating the amount of stuffs to be contained in the second frame based on a bit rate ratio between the first frame and the second frame; and a second control unit controlling a timing of reading out the first-frame frame data stored in the storage unit based on the second stuff information.

摘要翻译： 发送装置通过调整要存储在第二帧中的填充量来存储具有与第一帧不同的比特率的第二帧中的第一帧的帧数据。 发送装置包括：存储单元，存储第一帧帧数据; 第一控制单元，基于表示第一帧中包含的填充量的第一填充信息，控制将第一帧帧数据写入存储单元的定时; 算术和逻辑单元，基于第一帧和第二帧之间的比特率，获得指示要包含在第二帧中的填充量的第二填充信息; 以及第二控制单元，其基于第二填充信息控制读出存储在存储单元中的第一帧帧数据的定时。

公开(公告)号：US20120251127A1

公开(公告)日：2012-10-04

申请号：US13365819

申请日：2012-02-03

申请人： Toshiaki OHKUBO ,  Toru Katagiri ,  Hiroyuki Honma ,  Hiromichi Makishima ,  Hiroyuki Kitajima

发明人： Toshiaki OHKUBO ,  Toru Katagiri ,  Hiroyuki Honma ,  Hiromichi Makishima ,  Hiroyuki Kitajima

IPC分类号： H04B10/04

CPC分类号： H04J3/1652

摘要： An apparatus for mapping multiple lower-speed signal transmission frames to a higher-speed signal transmission frame. The apparatus includes buffers configured to buffer the lower-speed signal transmission frames, determination units configured to determine frequency justification information for the lower-speed signal transmission frames, a barrel shifter configured to receive signals output from the buffers, and a controller configured to control the barrel shifter to map the lower-speed signal transmission frames to the higher-speed signal transmission frame based on external settings for the respective lower-speed signal transmission frames and the frequency justification information determined by the determination units. When the minimum unit of the lower-speed signal transmission frames is a channel, the number of the buffers and the number of the determination units correspond to the maximum number of channels that can be multiplexed in the higher-speed signal transmission frame.

摘要翻译： 一种用于将多个低速信号传输帧映射到更高速度的信号传输帧的装置。 该装置包括被配置为缓冲低速信号传输帧的缓冲器，被配置为确定低速信号传输帧的频率调整信息的确定单元，被配置为接收从缓冲器输出的信号的桶形移位器，以及被配置为控制 桶形移位器基于各个低速信号传输帧的外部设置和由确定单元确定的频率对齐信息将低速信号传输帧映射到较高速度的信号传输帧。 当低速信号传输帧的最小单位是信道时，缓冲器的数量和确定单元的数量对应于在高速信号传输帧中可以多路复用的最大信道数。