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1.发明授权Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel 有权能够并行执行输入/输出和高速几何计算处理的几何处理器公开(公告)号：US06603481B1
公开(公告)日：2003-08-05
申请号：US09294002
申请日：1999-04-19
申请人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
发明人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： The geometry processor includes mutually independent first and second external interface ports connected to a host processor, and a rendering processor, respectively, and a geometry calculation core which processes a geometry calculation applied through the first external interface port from the host processor. The geometry calculation core includes a plurality of SIMD type floating point calculating units, a floating point power computing unit, an integer calculating unit, a controller responsive to an instruction from the host processor which controls the plurality of floating point calculating units, the floating point power computing unit and the integer calculating unit to process data from the host processor, and an output controller which outputs the processed data to the rendering processor through the second external interface port.
摘要翻译： 几何处理器包括分别连接到主机处理器和渲染处理器的相互独立的第一和第二外部接口端口以及处理通过第一外部接口端口从主机处理器应用的几何计算的几何计算核心。 几何计算核心包括多个SIMD型浮点计算单元，浮点计算单元，整数计算单元，响应于来自主处理器的控制多个浮点计算单元的指令的控制器，浮点 功率计算单元和用于处理来自主处理器的数据的整数计算单元，以及输出控制器，其通过第二外部接口端口将处理后的数据输出到渲染处理器。
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公开(公告)号：US06442627B1
公开(公告)日：2002-08-27
申请号：US09453547
申请日：1999-12-03
申请人： Hiroyasu Negishi , Junko Kobara , Yoshitsugu Inoue , Hiroyuki Kawai , Keijiro Yoshimatsu , Nelson Chan , Robert Streitenberger
发明人： Hiroyasu Negishi , Junko Kobara , Yoshitsugu Inoue , Hiroyuki Kawai , Keijiro Yoshimatsu , Nelson Chan , Robert Streitenberger
IPC分类号： G06F300
摘要： An output FIFO data transfer control device can comprise a geometric arithmetic core including one integer processing unit or IPU and a plurality of floating-point processing units or FPUs. Each processing unit includes an intermediate buffer or data output buffer for storing a data on an arithmetic result. When an instruction of data transfer from at least one of the plurality of processing units to one output FIFO is issued, a write/read pointer generating unit generates a write pointer identifying a specific location where data on an arithmetic result associated with the instruction is to be stored in the intermediate buffer of at least one of the plurality of processing units. The write/read pointer generating unit also generates a read pointer identifying a specific location where data is to be read out of the intermediate buffer of at least one of the plurality of processing units. A transfer mode setting unit sets a transfer mode identifying which at least one of the plurality of processing units is to transfer data on an arithmetic result, and sequentially furnishes a read enable signal to at least one of the plurality of processing units so as to read out the data from the intermediate buffer of at least one of the plurality of processing units.
摘要翻译： 输出FIFO数据传送控制装置可以包括包括一个整数处理单元或IPU以及多个浮点处理单元或FPU的几何运算核心。 每个处理单元包括用于存储关于算术结果的数据的中间缓冲器或数据输出缓冲器。 当发出从多个处理单元中的至少一个处理单元到一个输出FIFO的数据传送指令时，写入/读出指针生成单元产生一个写入指针，该指针识别与该指令相关联的算术结果的数据为 被存储在多个处理单元中的至少一个处理单元的中间缓冲器中。 写/读指针生成单元还生成识别要从多个处理单元中的至少一个的中间缓冲器读出数据的特定位置的读指针。 传送模式设置单元设置传送模式，其识别多个处理单元中的至少一个处理单元是在算术结果上传送数据，并且将读取使能信号顺序地提供给多个处理单元中的至少一个，以便读取 从多个处理单元中的至少一个的中间缓冲器输出数据。
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公开(公告)号：US06480873B1
公开(公告)日：2002-11-12
申请号：US09478004
申请日：2000-01-05
申请人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Robert Streitenberger , Keijiro Yoshimatsu , Hiroyasu Negishi
发明人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Robert Streitenberger , Keijiro Yoshimatsu , Hiroyasu Negishi
IPC分类号： G06F738
CPC分类号： G06F7/556
摘要： A power operation device comprises a bit operation unit or performing a bit shift operation on a logarithmic base bit string from a logarithm operation unit according to an input exponent bit string Y, and for furnishing the shifted logarithmic base bit string as a multiplication bit string. An exponent checking unit checks whether or not the input exponent bit string Y is the ith power of a base 2 where i is an integer, and, if so, furnishes a selection signal to direct selection of the multiplication bit string from the bit operation unit. A multiplication bit string selection unit selects and furnishes the multiplication bit string when it receives the selection signal from the exponent checking unit. In contrast, the multiplication bit string selection unit selects and furnishes another multiplication bit string from a multiplier otherwise. An exponential operation unit performs a base-2 exponential operation on the selected multiplication bit string from the multiplication bit string selection unit, i.e., computes 2Z where Z is the selected multiplication bit string, and furnishes the computed base-2 exponential value as the power operation-result XY.
摘要翻译： 电力操作装置包括位操作单元或者根据输入的指数位串Y从对数运算单元对对数基本位串执行位移操作，并将移位的对数基本位串提供为乘法位串。 指数检查单元检查输入指数位串Y是否是基数2的第i个幂，其中i是整数，如果是，则提供选择信号以从位操作单元直接选择乘法位串 。 乘法比特串选择单元当从指数检查单元接收到选择信号时，选择并提供乘法比特串。 相反，乘法比特串选择单元否则从乘数中选择并提供另一乘法比特串。 指数运算单元从乘法位串选择单元对所选择的乘法比特串执行基2指数运算，即计算2Z，其中Z是所选乘法位串，并将计算出的基2指数值作为幂 操作结果XY。
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4.发明授权Graphic processor having multiple geometric operation units and method of processing data thereby 有权具有多个几何运算单元的图形处理器和由此处理数据的方法公开(公告)号：US06795075B1
公开(公告)日：2004-09-21
申请号：US09685895
申请日：2000-10-11
IPC分类号： G06F1516
CPC分类号： G06T15/005
摘要： A graphic processor includes first and second buses and a plurality of geometric operation units having an output connected to the second bus, and a circuit to allocate a plurality of ordered data blocks formed of data to be operated upon to the plurality of geometric operation units, and an input of at least one of the plurality of geometric operation units is connected to the first bus. The plurality of geometric operation units include all arbitrating circuit to arbitrate the order of output between an output buffer to store a result of processing by the allocated data blocks and another geometric operation unit, and output data resulting from processing onto the second bus in an order corresponding to the sequence of the plurality of data blocks of data to be operated upon.
摘要翻译： 图形处理器包括第一和第二总线以及具有连接到第二总线的输出的多个几何运算单元，以及分配由多个几何运算单元运行的数据构成的多个有序数据块的电路， 并且所述多个几何运算单元中的至少一个的输入连接到所述第一总线。 多个几何运算单元包括用于仲裁输出缓冲器之间的输出顺序的所有仲裁电路，用于存储由分配的数据块和另一几何运算单元进行的处理结果，并且以按顺序将从处理得到的处理结果输出到第二总线上 对应于要被操作的数据的多个数据块的序列。
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5.发明授权公开(公告)号：US06711601B2
公开(公告)日：2004-03-23
申请号：US09775513
申请日：2001-02-05
IPC分类号： G06F7556
CPC分类号： G06F1/0307 , G06F1/035
摘要： A logarithmic arithmetic unit includes first logarithmic operation part multiplying an exponent part of floating-point data by a prescribed value, a logarithmic table memory outputting a logarithmic value corresponding to bit data expressing a digit higher than a prescribed digit of a fixed-point part of the floating-point data, divisional precision decision part deciding divisional precision on the basis of the exponent part, division part performing division on a dividend obtained by subtracting the bit data from the fixed-point part and a divisor of the bit data and obtaining a result of division of a number of digits set on the basis of the divisional precision, second logarithmic operation part obtaining the logarithmic value of a value obtained by dividing the fixed-point part by the bit data and sum operation part adding outputs from the first and second logarithmic operation parts and the logarithmic table memory to each other.
摘要翻译： 对数算术单元包括将浮点数据的指数部分乘以规定值的第一对数运算部，对数表存储器输出对应于与比特数据对应的对数值，比特数据表示高于定点部分的规定数位 所述浮点数据，分割精度判定部根据所述指数部判定分割精度，对所述定点部分减去所述位数据和所述位数据的除数进行除法而得到的除数， 基于分割精度设定的数位分割结果，第二对数运算部分求出通过将定点部分除以比特数据而获得的值的对数值和加法运算部分的加法运算部分，从第一和第 第二对数运算部分和对数表存储器。
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公开(公告)号：US07054979B2
公开(公告)日：2006-05-30
申请号：US09985009
申请日：2001-11-01
IPC分类号： G06F13/14
CPC分类号： H04L12/4625
摘要： The method of routing configuration accesses applied from the primary port to a plurality of secondary ports includes the steps of: distributing a plurality of configuration accesses received from the primary bus to the plurality of secondary ports in accordance with a predetermined algorithm, such that each of the devices on the secondary ports receives and responds to exactly a single access; and terminating configuration cycles after distributing the plurality of configuration accesses.
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7.发明授权First-in first-out data transfer control device having a plurality of banks 有权具有多个存储体的先进先出的数据传送控制装置公开(公告)号：US06697889B2
公开(公告)日：2004-02-24
申请号：US09778778
申请日：2001-02-08
IPC分类号： G06F1336
CPC分类号： G06F5/065
摘要： An FIFO data transfer control device includes an instruction analyzing portion for analyzing an instruction for data transfer to an FIFO storage device including a plurality of banks, and calculating an amount of data to be transferred; a data count portion for calculating, from the data amount calculated by the instruction analyzing portion, an amount of the data written in the bank being in an outputting state, and issuing a determination flag indicating whether the free space of the bank being in the outputting state satisfies predetermined conditions or not; and a full check portion for inhibiting processing of a next instruction until the determination flag sent from the data count portion or the full flag issued from the FIFO storage device is reset.
摘要翻译： FIFO数据传送控制装置包括指令分析部分，用于分析用于数据传送到包括多个存储体的FIFO存储装置的数据传输指令，并计算要传送的数据量; 数据计数部分，用于根据由指令分析部分计算的数据量计算写入处于输出状态的存储体中的数据量，并且发出指示所述存储体的存储空间是否在输出中的确定标志 状态满足预定条件; 以及用于禁止下一个指令的处理的完整检查部分，直到从数据计数部分发送的确定标志或从FIFO存储装置发出的完整标志被重置。
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公开(公告)号：US06675251B1
公开(公告)日：2004-01-06
申请号：US09551841
申请日：2000-04-18
IPC分类号： G06F1336
CPC分类号： G06F13/4059
摘要： A bridge includes a first port connected to a Primary bus, and second ports respectively connected to second buses. The first port includes a PCI master, a PCI slave and an AGP master. Each of the second ports includes a PCI master, a PCI target and an AGP Target. The bridge further includes a plurality of first-in-first-out memories forming asynchronous data paths between the first port and the second ports and arbitrators for arbitrating a contention between the transactions on the data paths formed by the first-in-first-out memories based on the protocols related to the transactions.
摘要翻译： 桥包括连接到主总线的第一端口和分别连接到第二总线的第二端口。 第一个端口包括一个PCI主站，一个PCI从站和一个AGP主站。 每个第二端口包括PCI主机，PCI目标和AGP目标。 桥还包括在第一端口和第二端口之间形成异步数据路径的多个先进先出存储器和仲裁器，用于仲裁由先进先出形成的数据路径上的事务之间的争用 基于与交易相关的协议的记忆。
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公开(公告)号：US06581087B1
公开(公告)日：2003-06-17
申请号：US09620472
申请日：2000-07-20
IPC分类号： G06F750
CPC分类号： G06F7/485
摘要： In a floating point adder adding received two floating point data together and subtracting one such data from the other, before their exponent parts are matched in digit by a digit match unit the two data have their exponent parts compared and also their fraction parts compared, and a result of each comparison and a sign of each data are used to code a relationship in magnitude between data corresponding to a clipping coordinate and the other data fed. A clip code generated depending on the previously obtained comparison results from exponent part and fraction part compare units, rather than depending on a zero flag according to a result of an addition or a subtraction and a sign of the result of the addition or the subtraction, can rapidly be generated without the circuit increased in scale.
摘要翻译： 在浮点加法器中，将接收到的两个浮点数据加在一起，并从另一个中减去一个这样的数据，在它们的指数部分通过数位匹配单元匹配数字之前，两个数据的比指数部分与其比例部分进行比较， 使用每个比较的结果和每个数据的符号来编码对应于剪切坐标的数据与馈送的其他数据之间的大小关系。 根据先前获得的指数部分和分数部分比较单位的比较结果生成的剪辑代码，而不是根据加法或减法的结果的零标志和加法或减法的结果的符号， 可以快速产生电路，而电路规模不会增加。
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10.发明授权
公开(公告)号：US5657485A
公开(公告)日：1997-08-12
申请号：US509940
申请日：1995-08-01
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F9/30065
摘要： The present invention is directed to a program control unit which enables a program control to achieve an efficient loop processing which does not immediately follow a loop instruction and which contains a start address and end address. In the program control unit, the start address and end address of a loop processing are stored in a register (start) (7) and a register (end) (8), respectively, in synchronization with a clock t1. The stored data "start" of the register (7) and the stored data "end" of the register (8) are inputted to a comparator (12) and a comparator (11), respectively. The comparator (12) compares the output from a delay program counter (18) with the data "start", and sets a flag f start when the comparison result indicates agreement and otherwise resets it. The comparator (11) compares the output from a delay program counter (18) with the data "end", and sets a flag f end when the comparison result indicates agreement and otherwise resets it.
摘要翻译： 本发明涉及一种程序控制单元，其使得程序控制能够实现不立即循环指令并且包含开始地址和结束地址的有效的循环处理。 在程序控制单元中，循环处理的起始地址和结束地址分别与时钟t1同步地存储在寄存器（起始）（7）和寄存器（结束）（8）中。 寄存器（7）的存储数据“开始”和寄存器（8）的存储数据“结束”分别输入到比较器（12）和比较器（11）。 比较器（12）将来自延迟程序计数器（18）的输出与数据“开始”进行比较，并且当比较结果指示一致时设置标志f开始，否则将其复位。 比较器（11）将来自延迟程序计数器（18）的输出与数据“结束”进行比较，并且当比较结果表示协议时设定标志f结束，否则将其复位。
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