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公开(公告)号：US20100309741A1
公开(公告)日：2010-12-09
申请号：US12859445
申请日：2010-08-19
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。
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公开(公告)号：US06687175B1
公开(公告)日：2004-02-03
申请号：US10149221
申请日：2002-06-10
IPC分类号： G11C700
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL.
摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。
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公开(公告)号：US08605478B2
公开(公告)日：2013-12-10
申请号：US13479240
申请日：2012-05-23
IPC分类号： G11C5/06
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译： 在用于DRAM存储单元的感测电路中，在位线BL和连接到存储器单元的局部位线LBL之间提供开关以隔离和耦合这些位线。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。
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公开(公告)号：US07126868B2
公开(公告)日：2006-10-24
申请号：US11118338
申请日：2005-05-02
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
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公开(公告)号：US07813156B2
公开(公告)日：2010-10-12
申请号：US12242164
申请日：2008-09-30
IPC分类号： G11C5/06
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL.
摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到位线LBL的锁存型读出放大器SA。
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公开(公告)号：US20060146623A1
公开(公告)日：2006-07-06
申请号：US11363085
申请日：2006-02-28
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置以隔离和耦合这些位线。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电 到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。
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公开(公告)号：US08199549B2
公开(公告)日：2012-06-12
申请号：US12859445
申请日：2010-08-19
IPC分类号： G11C5/06
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。
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公开(公告)号：US20050190588A1
公开(公告)日：2005-09-01
申请号：US11118338
申请日：2005-05-02
IPC分类号： G11C7/06 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C11/22
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。
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公开(公告)号：US20090027984A1
公开(公告)日：2009-01-29
申请号：US12242164
申请日：2008-09-30
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL.
摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到位线LBL的锁存型读出放大器SA。
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公开(公告)号：US07436722B2
公开(公告)日：2008-10-14
申请号：US11761642
申请日：2007-06-12
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置以隔离和耦合这些位线。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电 到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。
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