公开(公告)号：US20050141143A1

公开(公告)日：2005-06-30

申请号：US11009773

申请日：2004-12-10

申请人： Hiroyuki Ono ,  Hiroaki Suzuki ,  Toshio Sunaga ,  Hisatada Miyatake ,  Hideo Asano

发明人： Hiroyuki Ono ,  Hiroaki Suzuki ,  Toshio Sunaga ,  Hisatada Miyatake ,  Hideo Asano

IPC分类号： G11B5/39 ,  G11B5/127 ,  G11B5/33 ,  G11B5/40 ,  H01L43/08

CPC分类号： G11B5/39

摘要： In the case of magnetic head of magnetoresistance effect type whose breakdown voltage is as low as 0.3 V, it is impractical to ignore even a very small amount of static electricity that occurs during fabrication or use. In one embodiment, the desired magnetic head is produced by forming an SiO2 layer on a silicon slider, thereby forming an SOI substrate; forming on the SOI substrate circuits to protect a TMR element from overvoltage and a read-write circuit; forming field effect transistors from an Si semiconductor layer (formed by reduction of the SiO2 layer or epitaxial growth on the SiO2 layer); forming three electrodes (source, gate, drain) on the Si semiconductor layer; forming a Schottky diode by Schottky contact (metal) with the Si semiconductor layer; forming overvoltage protective circuits of aluminum wiring on the SOI substrate; and forming a TMR element.

摘要翻译： 在其击穿电压低至0.3V的磁阻效应型磁头的情况下，即使在制造或使用期间发生的非常少量静电也是不切实际的。 在一个实施例中，通过在硅滑块上形成SiO 2层来形成所需的磁头，由此形成SOI衬底; 在SOI衬底电路上形成以保护TMR元件免受过电压和读写电路; 从Si半导体层（通过SiO 2层的还原或SiO 2层上的外延生长形成）形成场效应晶体管; 在Si半导体层上形成三个电极（源极，栅极，漏极）; 通过与Si半导体层的肖特基接触（金属）形成肖特基二极管; 在SOI衬底上形成铝布线的过电压保护电路; 并形成TMR元件。

公开(公告)号：US07489482B2

公开(公告)日：2009-02-10

申请号：US11009773

申请日：2004-12-10

申请人： Hiroyuki Ono ,  Hiroaki Suzuki ,  Toshio Sunaga ,  Hisatada Miyatake ,  Hideo Asano

发明人： Hiroyuki Ono ,  Hiroaki Suzuki ,  Toshio Sunaga ,  Hisatada Miyatake ,  Hideo Asano

IPC分类号： G11B5/39

CPC分类号： G11B5/39

摘要： In the case of magnetic head of magnetoresistance effect type whose breakdown voltage is as low as 0.3 V, it is impractical to ignore even a very small amount of static electricity that occurs during fabrication or use. In one embodiment, the desired magnetic head is produced by forming an SiO2 layer on a silicon slider, thereby forming an SOI substrate; forming on the SOI substrate circuits to protect a TMR element from overvoltage and a read-write circuit; forming field effect transistors from an Si semiconductor layer (formed by reduction of the SiO2 layer or epitaxial growth on the SiO2 layer); forming three electrodes (source, gate, drain) on the Si semiconductor layer; forming a Schottky diode by Schottky contact (metal) with the Si semiconductor layer; forming overvoltage protective circuits of aluminum wiring on the SOI substrate; and forming a TMR element.

摘要翻译： 在其击穿电压低至0.3V的磁阻效应型磁头的情况下，即使在制造或使用期间发生的非常少量静电也是不切实际的。 在一个实施例中，通过在硅滑块上形成SiO 2层来制造所需的磁头，由此形成SOI衬底; 在SOI衬底电路上形成以保护TMR元件免受过电压和读写电路; 从Si半导体层形成场效应晶体管（通过SiO 2层的还原或SiO 2层上的外延生长形成）; 在Si半导体层上形成三个电极（源极，栅极，漏极）; 通过与Si半导体层的肖特基接触（金属）形成肖特基二极管; 在SOI衬底上形成铝布线的过电压保护电路; 并形成TMR元件。

公开(公告)号：US20080094882A1

公开(公告)日：2008-04-24

申请号：US11876607

申请日：2007-10-22

申请人： Hideo Asano ,  Koji Kitamura ,  Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki

发明人： Hideo Asano ,  Koji Kitamura ,  Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.

摘要翻译： 根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管; 其中所述存储器单元中的至少一些被布置成二维阵列; 第一互连线，沿着所述存储器阵列的第一方向延伸并且用作包含在每个存储单元中的选择晶体管的栅电极; 在存储器阵列的第一方向上延伸的第二互连线; 第三互连线，沿第二方向延伸; 其中所述存储器单元中的至少一些的所述磁阻元件夹在所述第二和第三互连线之间，其中所述第二互连线至少部分地沿着所述存储器单元中的特定一个的所有磁阻元件延伸。

公开(公告)号：US20060227600A1

公开(公告)日：2006-10-12

申请号：US11381578

申请日：2006-05-04

申请人： Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki ,  Hideo Asano ,  Koji Kitamura

发明人： Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki ,  Hideo Asano ,  Koji Kitamura

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines

摘要翻译： 根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管，其中存储单元被布置成二维阵列。 第一互连线在存储器阵列的第一方向上延伸，并且用作包含在每个存储单元中的选择晶体管的栅电极。 第二互连线在存储器阵列的第一方向上延伸。 第三互连线在第二方向上延伸。 至少一些存储单元的磁电阻元件夹在第二和第三互连线之间

公开(公告)号：US07511981B2

公开(公告)日：2009-03-31

申请号：US11876607

申请日：2007-10-22

申请人： Hideo Asano ,  Koji Kitamura ,  Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki

发明人： Hideo Asano ,  Koji Kitamura ,  Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki

IPC分类号： G11C5/08

CPC分类号： G11C11/16

摘要： A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.

摘要翻译： 根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管; 其中所述存储器单元中的至少一些被布置成二维阵列; 第一互连线，沿着所述存储器阵列的第一方向延伸并且用作包含在每个存储单元中的选择晶体管的栅电极; 在存储器阵列的第一方向上延伸的第二互连线; 第三互连线，沿第二方向延伸; 其中所述存储器单元中的至少一些的所述磁阻元件夹在所述第二和第三互连线之间，其中所述第二互连线至少部分地沿着所述存储器单元中的特定一个的所有磁阻元件延伸。

公开(公告)号：US06992924B2

公开(公告)日：2006-01-31

申请号：US10680051

申请日：2003-10-07

申请人： Hisatada Miyatake ,  Hiroshi Umezaki ,  Kohji Kitamura ,  Toshio Sunaga ,  Kohki Noda ,  Hideo Asano

发明人： Hisatada Miyatake ,  Hiroshi Umezaki ,  Kohji Kitamura ,  Toshio Sunaga ,  Kohki Noda ,  Hideo Asano

IPC分类号： G11C11/15

CPC分类号： G11C11/16 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5006

摘要： The invention provides methods and apparatus for for determining and providing optimum write bit line current and write word line current in an MRAM. A single reference potential is used to determine the values of the write line current and the bit line current. In determining the optimal values, asteroid curves representing bit line magnetic fields Hx generated by write bit line current IB and word line magnetic fields Hy generated by write word line current Iw for magnetization are considered, and an asteroid curve ACout is defined outside the asteroid curves of all memory cells taking manufacture variations and design margins into account. A write bit line current and a write word line current are selected such that the write current obtained by adding the write bit line current or currents and the write word line current, or the write power consumed by the bit line or lines and the write word line is minimized. Furthermore, in order to prevent multi-selection, the write bit line current and the write word line current are selected so that they generate a synthetic magnetic field on the curve between calculated points of the asteroid curve ACout.

摘要翻译： 本发明提供了用于在MRAM中确定和提供最佳写入位线电流和写入字线电流的方法和装置。 单个参考电位用于确定写入线电流和位线电流的值。 在确定最佳值时，表示通过写入位线电流I B和字线磁场H SUB生成的位线磁场H 的小行星曲线 考虑了用于磁化的写入字线电流I 产生的小行星曲线AC＆lt; SUB＆gt;被定义在所有存储器单元的小行星曲线之外，其采取制造变化和设计余量 考虑到 选择写位线电流和写字线电流，使得通过将写位线电流或电流和写字线电流相加而获得的写入电流或由位线或线消耗的写入功率和写入字 线最小化。 此外，为了防止多次选择，选择写入位线电流和写入字线电流，使得它们在小行星曲线AC的计算点之间的曲线上产生合成磁场， 。

公开(公告)号：US07349235B2

公开(公告)日：2008-03-25

申请号：US11381578

申请日：2006-05-04

申请人： Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki ,  Hideo Asano ,  Koji Kitamura

发明人： Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki ,  Hideo Asano ,  Koji Kitamura

IPC分类号： G11C5/08

CPC分类号： G11C11/16

摘要： A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.

摘要翻译： 根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管，其中存储单元被布置成二维阵列。 第一互连线在存储器阵列的第一方向上延伸，并且用作包含在每个存储单元中的选择晶体管的栅电极。 第二互连线在存储器阵列的第一方向上延伸。 第三互连线在第二方向上延伸。 至少一些存储单元的磁电阻元件夹在第二和第三互连线之间。

公开(公告)号：US20050073897A1

公开(公告)日：2005-04-07

申请号：US10964352

申请日：2004-10-12

申请人： Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki ,  Hideo Asano ,  Koji Kitamura

发明人： Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki ,  Hideo Asano ,  Koji Kitamura

IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/00

CPC分类号： G11C11/16

摘要： MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.

摘要翻译： MRAM具有在y方向上延伸的字线WLR和写入字线WLW，在x方向上延伸的写入/读取位线BLW / R和写入位线BLW，以及设置在这些交点处的存储单元MC 线条。 存储器MC包括子单元SC1和SC2。 子单元SC1包括磁阻元件MTJ1和MTJ2以及选择晶体管Tr1，子单元SC2包括磁阻元件MTJ3和MTJ4以及选择晶体管Tr2。 磁电阻元件MTJ1和MTJ2并联连接，磁电阻元件MTJ3和MTJ4也并联连接。 此外，子单元SC1和SC2串联连接在写/读位线BLW / R和地之间。

公开(公告)号：US06785154B2

公开(公告)日：2004-08-31

申请号：US10134100

申请日：2002-04-26

申请人： Toshio Sunaga ,  Hisatada Miyatake ,  Koji Kitamura ,  Hideo Asano ,  Kohki Noda ,  Hiroshi Umezaki

发明人： Toshio Sunaga ,  Hisatada Miyatake ,  Koji Kitamura ,  Hideo Asano ,  Kohki Noda ,  Hiroshi Umezaki

IPC分类号： G11C1700

CPC分类号： G11C11/15 ,  G11C2207/2263

摘要： A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline 32 and, for generating a stop signal for stopping a data write current supply to the bitline 32 and a write wordline 30 after data is written in an magnetic tunnel junction (MTJ) element 44. Further, when data to be written to the storage element is the same as the data already stored therein, no write current is supplied to the write wordline 30, thereby saving power.

摘要翻译： 本文公开了磁性随机存取存储器（MRAM）电路块及其访问方法，其包括用于感测通过位线32的数据写入电流的电路，并且用于产生用于停止向位线32的数据写入电流供应的停止信号 以及数据写入磁性隧道结（MTJ）元件44之后的写入字线30.此外，当要写入存储元件的数据与已经存储的数据相同时，不向写入字线提供写入电流 30，从而节省电力。

公开(公告)号：US06826076B2

公开(公告)日：2004-11-30

申请号：US10057369

申请日：2002-01-24

申请人： Hideo Asano ,  Koji Kitamura ,  Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki

发明人： Hideo Asano ,  Koji Kitamura ,  Hisatada Miyatake ,  Kohki Noda ,  Toshio Sunaga ,  Hiroshi Umezaki

IPC分类号： G11C1100

CPC分类号： G11C11/16

摘要： MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.

摘要翻译： MRAM具有在y方向上延伸的字线WLR和写入字线WLW，在x方向上延伸的写入/读取位线BLW / R和写入位线BLW，以及设置在这些交点处的存储单元MC 线条。 存储器MC包括子单元SC1和SC2。 子单元SC1包括磁阻元件MTJ1和MTJ2以及选择晶体管Tr1，子单元SC2包括磁阻元件MTJ3和MTJ4以及选择晶体管Tr2。 磁电阻元件MTJ1和MTJ2并联连接，磁电阻元件MTJ3和MTJ4也并联连接。 此外，子单元SC1和SC2串联连接在写/读位线BLW / R和地之间。