公开(公告)号：US07196701B2

公开(公告)日：2007-03-27

申请号：US09823927

申请日：2001-03-29

申请人： Yusuke Tsutsui ,  Makoto Kitagawa ,  Mitsugu Kobayashi ,  Hisao Uehara

发明人： Yusuke Tsutsui ,  Makoto Kitagawa ,  Mitsugu Kobayashi ,  Hisao Uehara

IPC分类号： G09G5/00

CPC分类号： G09G3/3611 ,  G09G3/3696 ,  G09G2330/021

摘要： A power supply circuit (300) for a display device such as a liquid crystal outputs a boosted supply voltage VDD2 during normal operation, and generates a non-boosted supply voltage VDD2 having a voltage lower than that during the normal display operation by controlling the switches for switching the output within the power supply circuit (300) during a power save mode. The non-boosted supply voltage is supplied to the analog circuits of a driving circuit (100) so that the power consumption at the analog circuits is reduced. By controlling the switch for switching the output within the power supply circuit and the supply of the power supply clock, the circuit can be switched, in the power save mode, to either a mode where a lower supply voltage is generated or to a mode where the power supply is turned off.

摘要翻译： 用于诸如液晶的显示装置的电源电路（300）在正常操作期间输出升压的电源电压VDD 2，并且通过控制产生具有低于正常显示操作期间电压的非升压电源电压VDD 2 用于在节电模式期间切换电源电路（300）内的输出的开关。 非升压电源电压被提供给驱动电路（100）的模拟电路，使得模拟电路的功耗降低。 通过控制用于切换电源电路内的输出的开关和电源时钟的供给，可以在省电模式下将电路切换到产生较低电源电压的模式或者其中 电源关闭。

公开(公告)号：US6127991A

公开(公告)日：2000-10-03

申请号：US969142

申请日：1997-11-12

申请人： Hisao Uehara ,  Mitsugu Kobayashi ,  Makoto Kitagawa ,  Yusuke Tsutsui

发明人： Hisao Uehara ,  Mitsugu Kobayashi ,  Makoto Kitagawa ,  Yusuke Tsutsui

IPC分类号： G09G3/20 ,  G09G3/28

CPC分类号： G09G3/2029 ,  G09G3/2022 ,  G09G3/288 ,  G09G2320/066 ,  G09G2320/0673

摘要： There is proposed is a method of controlling a flat panel display apparatus for multi-gradation display in which a data determination portion and a subfield control portion are provided. Based on a most significant bit or an upper bit of original image data, it is determined in which one of two or more divided gradation groups the original image data is included, to select a combination of subfields in accordance with a gradation-brightness characteristic of the belonging gradation group. Using a complementary relationship with human visibility, a difference in brightness between the gradations in a low-order brightness region is reduced, and a difference in brightness between the gradations in a high-order brightness region is enlarged. Therefore, a density of brightness is uniformly recognized visually over all the brightness regions, and a good quality of display can be obtained.

摘要翻译： 提出了一种控制用于多级显示的平板显示装置的方法，其中提供了数据确定部分和子场控制部分。 基于原始图像数据的最高有效位或较高位，确定包含原始图像数据的两个或更多个分割灰度组中的哪一个，根据灰度级亮度特性来选择子场的组合 归属等级组。 使用与人类可见度的互补关系，降低了低阶亮度区域中的灰度之间的亮度差异，并且放大了高阶亮度区域中的灰度之间的亮度差。 因此，在所有的亮度区域，视觉上均匀地识别亮度的浓度，并且可以获得良好的显示质量。

公开(公告)号：US06278496B1

公开(公告)日：2001-08-21

申请号：US09168773

申请日：1998-10-08

申请人： Makoto Kitagawa ,  Mitsugu Kobayashi ,  Makoto Fujioka ,  Yusuke Tsutsui ,  Hisao Uehara

发明人： Makoto Kitagawa ,  Mitsugu Kobayashi ,  Makoto Fujioka ,  Yusuke Tsutsui ,  Hisao Uehara

IPC分类号： H04N5202

CPC分类号： H04N5/202 ,  G09G3/2059 ,  G09G3/3648 ,  G09G2320/0276 ,  G09G2320/0606 ,  G09G2320/0626 ,  G09G2320/066 ,  H04N9/69

摘要： In the &ggr; correction circuit, a crossover point arithmetic processing unit performs arithmetic processing for each region on crossover points y in the output data direction of a &ggr; correction crossover line based on a plurality of slope data A respectively specified for each of a plurality of regions and crossover point positions X in the input data direction set in advance. A 5-to-4 encoder and a selector select one of a plurality of slope data A respectively specified for each of a plurality of regions and one result B of the results y of arithmetic processing on said crossover points based on the upper bits of input data, a flag encoder and another selector calculate the difference &Dgr;X from a crossover point position in the input data direction to the input data in the region to which input data belongs, and an arithmetic processing unit multiples the above difference &Dgr;X by the selected slope A, adds the multiplication result to the value of the selected crossover point position B in the output data direction, and outputs that value as a &ggr; correction value. Consequently, even if the number of crossover lines for digital &ggr; correction increases, arithmetic processing is simplified. When an image data processing apparatus is used, a pseudo gray scale processing circuit may be provided in a later stage of this &ggr; correction circuit to decrease the number of data bits.

摘要翻译： 在伽马校正电路中，交叉点算术处理单元基于分别为多个区域中的每一个指定的多个斜率数据A，对伽马校正交叉线的输出数据方向上的交叉点y上的各区域进行运算处理 并在预先设定的输入数据方向上的交叉点位置X。 5对4编码器和选择器选择分别为多个区域中的每一个指定的多个斜率数据A中的一个，以及基于输入的较高位的所述交叉点上的算术处理结果y的一个结果B 数据，标志编码器​​和另一个选择器从输入数据方向上的交叉点位置到输入数据所属的区域中的输入数据计算差DELTAX，并且运算处理单元将上述差DELTAX乘以所选择的斜率A ，将乘法结果与输出数据方向上所选交叉点位置B的值相加，并输出该值作为伽马校正值。 因此，即使用于数字伽马校正的交叉线的数量增加，也能够简化算术处理。 当使用图像数据处理装置时，可以在该伽马校正电路的后期提供伪灰度级处理电路以减少数据比特数。

公开(公告)号：US6118905A

公开(公告)日：2000-09-12

申请号：US591837

申请日：1996-01-19

申请人： Hisao Uehara ,  Mitsugu Kobayashi ,  Makoto Fujioka ,  Kenji Saiki ,  Makoto Kitagawa ,  Yusuke Tsutsui

发明人： Hisao Uehara ,  Mitsugu Kobayashi ,  Makoto Fujioka ,  Kenji Saiki ,  Makoto Kitagawa ,  Yusuke Tsutsui

IPC分类号： H04N1/40 ,  G06T5/00 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/36 ,  H04N1/405 ,  H04N1/56 ,  H04N1/60 ,  G06K9/36 ,  G06K9/38 ,  G06K9/46

CPC分类号： G09G3/2059 ,  H04N1/56 ,  G09G2320/0613

摘要： An image processing apparatus detects, in step 1, whether or not differences between currently supplied image data and image data of a previous pixel are more than a predetermined value m, and identifies a border of a computer-created image or a natural image, where a brightness level differs from the remaining area of the image, when the differences are more than the predetermined value m. Conversely, when the differences are less than the predetermined value m, the image processing apparatus checks, in step 2, whether image data at a pixel before and a pixel two before the current pixel are identical with respect to the color components constituting the color image. When the differences are not all zero, it is checked whether or not the image data at a pixel before the current pixel and the image data at the current pixel are all zero. When the image data are not identical, the color image is identified as being a natural image. When the image data are identical, the color image is identified as being a computer-created image. In step 3, the computer-created image is checked as to whether it is a 2-pixel checkered image.

摘要翻译： 图像处理装置在步骤1中检测当前提供的图像数据和先前像素的图像数据之间的差异是否大于预定值m，并且识别计算机创建的图像或自然图像的边界，其中 当差值大于预定值m时，亮度级别与图像的剩余区域不同。 相反，当差小于预定值m时，图像处理装置在步骤2中检查在当前像素之前的像素之前的像素数据和相对于构成彩色图像的色彩分量相同的像素之间的图像数据 。 当差异不全部为零时，检查当前像素之前的像素处的图像数据和当前像素处的图像数据是否全部为零。 当图像数据不相同时，彩色图像被识别为自然图像。 当图像数据相同时，彩色图像被识别为计算机创建的图像。 在步骤3中，检查计算机创建的图像是否是2像素方格图像。

公开(公告)号：US06891427B2

公开(公告)日：2005-05-10

申请号：US09823328

申请日：2001-03-29

申请人： Yusuke Tsutsui ,  Makoto Kitagawa ,  Mitsugu Kobayashi ,  Hisao Uehara

发明人： Yusuke Tsutsui ,  Makoto Kitagawa ,  Mitsugu Kobayashi ,  Hisao Uehara

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H02M1/36 ,  H02M3/07 ,  G09G5/00

CPC分类号： H02M1/36 ,  G09G3/3696 ,  H02M3/07

摘要： A driving circuit of a display device such as a liquid crystal generates power supply clocks (1 and 2) based on a system clock during the normal display operation which is not a power save mode. The generated power supply clocks are supplied, directly or after inversion, to the switches (SW1 through SW4 (and SW5 through SW8)) in a charge pump type power supply circuit (300) for switching the connection of capacitors (C1 and C2 (and C11 and C12)) in the power supply circuit (300). In this manner, supply voltages VDD2 and VDD3 which function as the driving power supply for a driving circuit (100) and a display panel (200) can be obtained at the power supply circuit (300) by boosting the input voltage Vin. The driving circuit (100) stops supply of the power supply clocks to the power supply circuit (300) when a transition to the power save mode is instructed and a power save control signal generated by a CPU I/F circuit (16) is changed, thereby suspending generation of the supply voltage an consumption of power consumption at the circuit and display panel.

摘要翻译： 诸如液晶的显示装置的驱动电路在不是省电模式的正常显示操作期间基于系统时钟产生电源时钟（1和2）。 在用于切换电容器（C）的连接的电荷泵型电源电路（300）中，将所产生的电源时钟直接或反转后提供给开关（SW 1至SW 4（和SW 5至SW 8）） 1和C 2（和C 11和C 12））。 以这种方式，通过升压输入电压Vin，可以在电源电路（300）获得用作驱动电路（100）和显示面板（200）的驱动电源的电源电压VDD 2和VDD 3。 驱动电路（100）在指示向省电模式的转变时停止向电源电路（300）供给电源时钟，并且由CPU I / F电路（16）产生的省电控制信号发生变化 从而暂停生成电源电压消耗电路和显示面板的功耗。

公开(公告)号：US06329980B1

公开(公告)日：2001-12-11

申请号：US09049487

申请日：1998-03-27

申请人： Hisao Uehara ,  Mitsugu Kobayashi ,  Yusuke Tsutsui

发明人： Hisao Uehara ,  Mitsugu Kobayashi ,  Yusuke Tsutsui

IPC分类号： G09G500

CPC分类号： G09G3/3611 ,  G09G3/20 ,  G09G3/3648 ,  G09G2310/0297 ,  G09G2320/0209

摘要： A signal driving circuit for an active matrix type display device having display pixels arranged in a matrix, comprises a signal waveform correcting circuit receiving an input pixel signal for generating a corrected output pixel signal to the display device, said signal waveform correcting circuit including a delay circuit for generating a delay signal, a difference calculating circuit for calculating a difference signal between the input pixel signal and the delay signal, and a correction circuit for generating the corrected output pixel signal based upon the difference signal and the input pixel signal, wherein a portion of the waveform amplitude of the corrected output pixel signal is formed by adjusting a corresponding portion of the waveform amplitude of the input pixel signal based upon the difference signal.

摘要翻译： 一种用于具有排列成矩阵的显示像素的有源矩阵型显示装置的信号驱动电路，包括信号波形校正电路，接收用于向显示装置产生经校正的输出像素信号的输入像素信号，所述信号波形校正电路包括延迟 用于产生延迟信号的电路，用于计算输入像素信号和延迟信号之间的差分信号的差分计算电路，以及用于基于差分信号和输入像素信号产生校正的输出像素信号的校正电路，其中a 校正输出像素信号的波形幅度的一部分是通过基于差分信号调整输入像素信号的波形幅度的相应部分来形成的。

公开(公告)号：US07190381B2

公开(公告)日：2007-03-13

申请号：US10462813

申请日：2003-06-17

申请人： Yusuke Tsutsui ,  Makoto Kitagawa ,  Mitsugu Kobayashi

发明人： Yusuke Tsutsui ,  Makoto Kitagawa ,  Mitsugu Kobayashi

IPC分类号： G09G5/00

CPC分类号： G09G3/3655 ,  G09G3/006 ,  G09G5/003 ,  G09G2300/08 ,  G09G2320/0223 ,  G09G2320/0693 ,  G09G2370/042 ,  Y10S345/904

摘要： A liquid crystal display device has a liquid crystal panel, a DA converter for generating a common electrode signal to be applied to a common electrode of a liquid crystal, and a non-volatile memory for encoding an optimum value of the common electrode signal into an ID code and storing the ID code therein. The DA converter generates the optimum common electrode signal corresponding to the ID code read out from the non-volatile memory. A liquid crystal panel manufacturer ships the liquid crystal panel in which the optimum value of the common electrode signal is encoded into the ID code and stored in the non-volatile memory in an inspecting process. The assembling manufacturer using the liquid crystal panel can easily set the optimum value of the common electrode signal. Furthermore, the liquid crystal display device has a CPU decoding the ID code read out from the non-volatile memory. Alternatively, it is possible to supply a data of a value of the common electrode signal to a user of the liquid crystal. The user adjusts the common electrode signal generating circuit by using the data of the value of the common electrode signal.

摘要翻译： 液晶显示装置具有：液晶面板，用于产生要施加到液晶的公共电极的公共电极信号的DA转换器;以及用于将公共电极信号的最佳值编码为 ID代码并存储其中的ID代码。 DA转换器产生对应于从非易失性存储器读出的ID码的最佳公共电极信号。 在检查过程中，液晶面板制造商将公共电极信号的最佳值编码为ID代码并存储在非易失性存储器中的液晶面板。 使用液晶面板的组装制造商可以容易地设定公共电极信号的最佳值。 此外，液晶显示装置具有对从非易失性存储器读出的ID码进行解码的CPU。 或者，可以向液晶的用户提供公共电极信号的值的数据。 用户通过使用公共电极信号的值的数据来调整公共电极信号发生电路。

公开(公告)号：US5990855A

公开(公告)日：1999-11-23

申请号：US813465

申请日：1997-03-10

申请人： Mitsugu Kobayashi ,  Hisao Uehara ,  Makoto Kitagawa

发明人： Mitsugu Kobayashi ,  Hisao Uehara ,  Makoto Kitagawa

IPC分类号： G09G3/20 ,  G09G3/36 ,  H04N5/66 ,  H04N9/30

CPC分类号： G09G3/2059 ,  G09G2360/16 ,  G09G3/3611 ,  H04N5/66 ,  H04N9/30

摘要： There is provided an image information process apparatus to be applied to a display for displaying bit image display data for each pixel, for enabling the display to display continuous tones in an error diffusion manner based on P bit image data, P being larger than L. This apparatus includes a plurality of adding circuits to which a plurality of P bit image data are concurrently supplied. A predetermined lower bit of an added result at respective adding circuits is used as error data supplied to the next adjacent adding circuit. An error data holding circuit holds a predetermined lower bit of an output from an adding circuit corresponding to the last column pixel in image data supplied. It then supplies the lower bit held to an adding circuit corresponding to the top front column pixel of the image data supplied. With this arrangement, a display which is capable of displaying images based on digital data of a limited number of bits displays in a pseudo manner continuous tones expressed using a higher number of bits than the limited number. In addition, performance and processing speed of image information processing are improved.

摘要翻译： 提供了一种应用于显示器的图像信息处理装置，用于显示每个像素的位图像显示数据，以使得显示器能够以P位图像数据P大于L的方式以误差扩散方式显示连续色调。 该装置包括多个附加电路，多个P位图像数据被同时提供给该多个加法电路。 作为向下一个相邻加法电路提供的误差数据，使用各加法电路的相加结果的预定的低位。 误差数据保持电路保持来自与提供的图像数据中的最后列像素对应的加法电路的输出的预定的低位。 然后，将保持的低位提供给与提供的图像数据的顶部前列像素相对应的加法电路。 利用这种布置，能够以有限位数的数字数据显示图像的显示器以伪限制的数量显示以连续色调的连续色调。 此外，提高了图像信息处理的性能和处理速度。

公开(公告)号：US07091946B2

公开(公告)日：2006-08-15

申请号：US10454777

申请日：2003-06-05

申请人： Yusuke Tsutsui ,  Makoto Kitagawa ,  Mitsugu Kobayashi

发明人： Yusuke Tsutsui ,  Makoto Kitagawa ,  Mitsugu Kobayashi

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G2310/0248 ,  G09G2310/04 ,  G09G2330/021

摘要： A mask circuit is provided in a display device having a plurality of pixels. The mask circuit supplies a video signal to each of the pixels in a partial display area selected based on a display area selection signal, and prevents the supply of the video signal to each of the pixels in a background display area. Accordingly, this display device displays an arbitrary pattern at an arbitrary position of the display panel of the display device. In addition, an inverting controlling circuit is provided for inverting the background display signal supplied to each of the pixels in the background display area for each frame. The power consumption of the display device can be reduced.

摘要翻译： 在具有多个像素的显示装置中设置有掩模电路。 掩模电路将视频信号提供给基于显示区域选择信号选择的部分显示区域中的每个像素，并且防止视频信号提供给背景显示区域中的每个像素。 因此，该显示装置在显示装置的显示面板的任意位置显示任意图案。 此外，提供反转控制电路，用于反转提供给每帧的背景显示区域中的每个像素的背景显示信号。 可以减少显示装置的功耗。

公开(公告)号：US06876365B1

公开(公告)日：2005-04-05

申请号：US09604301

申请日：2000-06-26

申请人： Yusuke Tsutsui ,  Mitsugu Kobayashi ,  Makoto Kitagawa

发明人： Yusuke Tsutsui ,  Mitsugu Kobayashi ,  Makoto Kitagawa

IPC分类号： G06F13/00 ,  H04N3/14

CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G3/30 ,  G09G3/3666 ,  G09G2310/0221 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2340/0492 ,  G09G2352/00

摘要： An input digital video signal is allotted by a first multiplexer (310) between regions of a display area to be driven in a dividing manner and is sequentially input to a first memory portion (30A) or a second memory portion (30B). Each of the first and second memory portions (30A and 30B) comprises an input-side line memory (32) composed of, for example, 400-stage input side shift register to which said digital video signal is sequentially input, and an output-side line memory (34) for receiving the data transferred in parallel from the input line memory (32) to serially output the stored data from a selected one of output portions (Out1-4) provided at the 320th, 256th or first stage FF34. The output portion of the memory (34) is thus selected by selectors (380A, 380B) in accordance with the number of pixels in the horizontal direction of the LCD panel, such that LCD panels having the different numbers of pixels can be driven with the same structure. The output-side line memory (34) further includes a data shift direction switching circuit. By controlling the switching circuit and selecting the output at the first stage FF34(Out4) in the 400 stages, the data from the output-side line memory (34) can be output in the order opposite to the input order into the input-side line memory (32).

摘要翻译： 输入数字视频信号由待分割的驱动的显示区域的区域之间的第一多路复用器（310）分配，并被顺序地输入到第一存储器部分（30A）或第二存储器部分（30B）。 第一和第二存储器部分（30A和30B）中的每一个包括由例如顺序地输入所述数字视频信号的400级输入侧移位寄存器构成的输入侧行存储器（32） 侧面存储器（34），用于接收从输入行存储器（32）并行传送的数据，以便从设置在第320，256或第一级FF34的输出部分（Out1-4）中选择的一个输出存储的数据。 因此，存储器（34）的输出部分根据LCD面板的水平方向的像素数由选择器（380A，380B）选择，使得具有不同像素数的LCD面板可以用 相同的结构。 输出侧线存储器（34）还包括数据移位方向切换电路。 通过控制开关电路并在400级中选择第一级FF34（Out4）的输出，来自输出侧行存储器（34）的数据可以以与输入顺序相反的顺序输出到输入侧 行存储器（32）。