公开(公告)号：US06342782B1

公开(公告)日：2002-01-29

申请号：US09623197

申请日：2000-10-13

申请人： Hisashi Yamaguchi ,  Tadashi Yasue

发明人： Hisashi Yamaguchi ,  Tadashi Yasue

IPC分类号： H03H100

CPC分类号： G09G3/3696 ,  G09G2330/021

摘要： A power supply device for driving liquid crystal which generates four liquid crystal drive voltages V1 and V4 between first and second reference voltages, the power supply device comprising: a voltage division circuit 102 which divides a voltage between voltages between voltages V1 and V5 and generates four pairs of first voltages NV1 to NV4 and second voltages PV1 to PV4; and four impedance conversion circuits 103 and 104 which generate impedance converted liquid crystal drive voltages V1 to V4 based on the four pairs of the first and second voltages. Each impedance conversion circuit comprises voltage follower type of differential amplifier circuits 120 and 110 to which a pair of the first and second voltages is input, and an output circuit 130 which is driven by the differential amplification circuits. The N-type transistor 134 and P-type transistor 132 in the output circuit are independently driven by the first and second output voltages VN, VP from the differential amplification circuits 120 and 110.

公开(公告)号：US06476591B2

公开(公告)日：2002-11-05

申请号：US09977941

申请日：2001-10-17

申请人： Hisashi Yamaguchi ,  Tadashi Yasue

发明人： Hisashi Yamaguchi ,  Tadashi Yasue

IPC分类号： H03H106

CPC分类号： G09G3/3696 ,  G09G2330/021

摘要： A power supply device for driving liquid crystal which generates four liquid crystal drive voltages V1 and V4 between first and second reference voltages, the power supply device comprising: a voltage division circuit 102 which divides a voltage between voltages between voltages V1 and V5 and generates four pairs of first voltages NV1 to NV4 and second voltages PV1 to PV4; and four impedance conversion circuits 103 and 104 which generate impedance converted liquid crystal drive voltages V1 to V4 based on the four pairs of the first and second voltages. Each impedance conversion circuit comprises voltage follower type of differential amplifier circuits 120 and 110 to which a pair of the first and second voltages is input, and an output circuit 130 which is driven by the differential amplification circuits. The N-type transistor 134 and P-type transistor 132 in the output circuit are independently driven by the first and second output voltages VN, VP from the differential amplification circuits 120 and 110.

摘要翻译： 一种用于驱动液晶的电源装置，其在第一和第二参考电压之间产生四个液晶驱动电压V1和V4，所述电源装置包括：分压电路102，其分压电压V1和V5之间的电压，并产生四个 一对第一电压NV1至NV4和第二电压PV1至PV4; 以及基于四对第一和第二电压产生阻抗转换的液晶驱动电压V1至V4的四个阻抗转换电路103和104。 每个阻抗转换电路包括输入一对第一和第二电压的电压跟随器类型的差分放大器电路120和110，以及由差分放大电路驱动的输出电路130。 输出电路中的N型晶体管134和P型晶体管132由差分放大电路120和110的第一和第二输出电压VN，VP独立地驱动。

公开(公告)号：US06144314A

公开(公告)日：2000-11-07

申请号：US989296

申请日：1997-12-11

申请人： Tadashi Yasue

发明人： Tadashi Yasue

IPC分类号： H04M1/66 ,  G08B5/22 ,  G08B13/14 ,  H04M1/673 ,  H04Q7/14

CPC分类号： G08B5/229 ,  G08B13/1436

摘要： A wireless selective-call receiver makes use of detection or absence of any to-and-fro movement of the receiver indicating that the receiver has been left somewhere thereby improving the security function of the receiver. When a motion detector detects no continuous shaky movement of the receiver, the message received by the receiver is stored in memory. A controller comprises a first control section which operates in a no movement condition, a second control section which operates in a moving condition, and a switching means for switching from the first control section to the second control section and vice versa. In the absence of the to-and-fro movement of the receiver (for example, the receiver is put away from the owner's body to be left on the desk), any access through a button inputting console and external interface except inputting a password is rejected. The message received is stored in memory, and not given on display, thereby preventing pieces of private information from leaking. In the absence of the shaky movement of the receiver the sound-making section alarms a sound at regular intervals, and an emergency contact address or telephone number is exhibited on display. Thus, the receiver once lost can be returned to the owner easily while maintaining security of information stored in the memory.

摘要翻译： 无线选呼接收机利用接收机的任何来回移动的检测或不存在，指示接收机已经被留在某处，从而改善接收机的安全功能。 当运动检测器检测到接收器没有连续的抖动运动时，由接收器接收的消息存储在存储器中。 控制器包括在无移动状态下操作的第一控制部分，在移动状态下操作的第二控制部分，以及用于从第一控制部分切换到第二控制部分的切换装置，反之亦然。 在没有接收机的来回移动的情况下（例如，接收器被放置在所有者的身体上以留在桌面上），除了输入密码之外，通过按钮输入控制台和外部接口的任何访问是 拒绝。 收到的消息存储在内存中，不在显示屏上，从而防止私人信息泄露。 在没有接收机摇动运动的情况下，制音部分定期发出声音，并且显示紧急联系地址或电话号码。 因此，一旦丢失的接收器可以容易地返回给所有者，同时保持存储在存储器中的信息的安全性。

公开(公告)号：US20050212826A1

公开(公告)日：2005-09-29

申请号：US11075692

申请日：2005-03-10

申请人： Masafumi Fukuda ,  Tadashi Yasue

发明人： Masafumi Fukuda ,  Tadashi Yasue

IPC分类号： G02F1/133 ,  G06F3/14 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/10 ,  G09G5/393

CPC分类号： G06F3/1415 ,  G06F11/1032 ,  G09G5/006 ,  G09G5/393 ,  G09G2310/0205 ,  G09G2310/027

摘要： A display driver includes: a parity generation circuit which generates s-bit parity data for n-bit display data input through a processor interface, combines the n-bit display data and the s-bit parity data, and outputs the combined n-bit display data and s-bit parity data to a display memory as (n+s)-bit display data; a parity check circuit which performs data error detection for the (n+s)-bit display data sequentially input from the display memory in units of (n+s) bits, and outputs the n-bit display data; at least one decoder which decodes the n-bit display data output from the parity check circuit; a plurality of latch circuits which latch the data decoded by the decoder; and a plurality of data line driver sections which drive data lines of a display panel based on the data latched by the latch circuits.

摘要翻译： 显示驱动器包括：奇偶校验生成电路，其生成通过处理器接口输入的n位显示数据的s位奇偶校验数据，组合n位显示数据和s位奇偶校验数据，并输出组合的n位 将显示数据和s位奇偶校验数据作为（n + s）位显示数据显示到显示存储器; 奇偶校验电路，以（n + s）位为单位对从显示存储器顺序输入的（n + s）位显示数据进行数据检错，输出n位显示数据; 至少一个解码器，对从奇偶校验电路输出的n位显示数据进行解码; 多个锁存电路，锁存由解码器解码的数据; 以及多个数据线驱动器部分，其基于由锁存电路锁存的数据驱动显示面板的数据线。

公开(公告)号：US20050212788A1

公开(公告)日：2005-09-29

申请号：US11085157

申请日：2005-03-22

申请人： Masafumi Fukuda ,  Tadashi Yasue

发明人： Masafumi Fukuda ,  Tadashi Yasue

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/34 ,  G09G5/395

CPC分类号： G09G5/346 ,  G09G3/20 ,  G09G3/2025 ,  G09G5/395 ,  G09G2310/0205 ,  G09G2310/027 ,  G09G2310/0283 ,  G09G2352/00 ,  G09G2360/12

摘要： A display driver including: a decoder which decodes n-bit display data (n is an integer greater than one) sequentially input from a display memory in units of n bits; a plurality of latch circuits which latch output data from the decoder, and a pluality of data line driver sections which drive data lines of a display panel based on the data latched by the latch circuits. The n-bit display data is read from the display memory and output to the decor by performing wordline control once for the display memory. The decoder squentially outputs the decoded n-bit display data to the latch circuits. The data line driver sections drive the data lines after the decoded data has been stored in the latch circuits.

摘要翻译： 一种显示驱动器，包括：以n位为单位从显示存储器顺序输入的n位显示数据（n为大于1的整数）的解码器; 锁存来自解码器的输出数据的多个锁存电路，以及基于由锁存电路锁存的数据驱动显示面板的数据线的数据线驱动器部分的pluality。 通过对显示存储器执行一次字线控制，从显示存储器读取n位显示数据并输出到装饰。 解码器将解码的n位显示数据极大地输出到锁存电路。 数据线驱动器部分在解码数据已经存储在锁存电路中之后驱动数据线。

公开(公告)号：US20050212785A1

公开(公告)日：2005-09-29

申请号：US11075857

申请日：2005-03-10

申请人： Masafumi Fukuda ,  Tadashi Yasue

发明人： Masafumi Fukuda ,  Tadashi Yasue

IPC分类号： G09G3/20 ,  G09G3/36 ,  G09G5/34 ,  G09G5/395

CPC分类号： G09G5/395 ,  G09G3/20 ,  G09G3/2025 ,  G09G5/346 ,  G09G2310/0205 ,  G09G2310/027 ,  G09G2310/0283 ,  G09G2352/00 ,  G09G2360/12

摘要： A display driver includes: a decoder which decodes n-bit (n is an integer greater than one) display data sequentially input from a display memory in units of n bits; a plurality of latch circuits which latch output data of the decoder; an address decoder which generates a latch pulse for the latch circuits to latch output from the decoder; and a plurality of data line driver sections. The n-bit display data is read from the display memory and input to the decoder by performing wordline control once. The decoder decodes the n-bit display data, and sequentially outputs the decoded data to the latch circuits. The address decoder outputs the latch pulse to one of the latch circuits selected based on address information on the display memory when the n-bit display data is read and storage destination designation information arbitrarily set from a control circuit.

摘要翻译： 显示驱动器包括：解码器，其以n位为单位解码从显示存储器顺序输入的n位（n是大于1的整数）显示数据; 多个锁存电路，其锁存解码器的输出数据; 地址解码器，其产生用于锁存电路的锁存脉冲以锁存来自解码器的输出; 和多个数据线驱动器部分。 通过执行字线控制一次，从显示存储器读取n位显示数据并输入到解码器。 解码器对n位显示数据进行解码，并且将解码的数据顺序地输出到锁存电路。 当读出n位显示数据时，地址解码器将锁存脉冲输出到基于显示存储器上的地址信息选择的一个锁存电路，并且从控制电路任意设置存储目的地指定信息。

公开(公告)号：US20110157130A1

公开(公告)日：2011-06-30

申请号：US12975907

申请日：2010-12-22

申请人： Tadashi Yasue

发明人： Tadashi Yasue

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/2077 ,  G09G3/2011 ,  G09G3/2018 ,  G09G3/2029 ,  G09G3/3625 ,  G09G2310/0205

摘要： A driving method of an electro optical device for driving with an Multi Line Selection driving method includes a gradation parameter assigning step of assigning display data of N bits (N is an integer equal to or larger than two) to a gradation parameter of M bits (N

摘要翻译： 用于通过多线选择驱动方法驱动的电光装置的驱动方法包括：灰度参数分配步骤，将N位（N是等于或大于2的整数）的显示数据分配给M位的灰度参数（ N

公开(公告)号：US07471302B2

公开(公告)日：2008-12-30

申请号：US11075692

申请日：2005-03-10

申请人： Masafumi Fukuda ,  Tadashi Yasue

发明人： Masafumi Fukuda ,  Tadashi Yasue

IPC分类号： G09G5/10

CPC分类号： G06F3/1415 ,  G06F11/1032 ,  G09G5/006 ,  G09G5/393 ,  G09G2310/0205 ,  G09G2310/027

摘要： A display driver includes: a parity generation circuit which generates s-bit parity data for n-bit display data input through a processor interface, combines the n-bit display data and the s-bit parity data, and outputs the combined n-bit display data and s-bit parity data to a display memory as (n+s)-bit display data; a parity check circuit which performs data error detection for the (n+s)-bit display data sequentially input from the display memory in units of (n+s) bits, and outputs the n-bit display data; at least one decoder which decodes the n-bit display data output from the parity check circuit; a plurality of latch circuits which latch the data decoded by the decoder; and a plurality of data line driver sections which drive data lines of a display panel based on the data latched by the latch circuits.

摘要翻译： 显示驱动器包括：奇偶校验生成电路，其生成通过处理器接口输入的n位显示数据的s位奇偶校验数据，组合n位显示数据和s位奇偶校验数据，并输出组合的n位 将显示数据和s位奇偶校验数据作为（n + s）位显示数据显示到显示存储器; 奇偶校验电路，以（n + s）位为单位对从显示存储器顺序输入的（n + s）位显示数据进行数据检错，输出n位显示数据; 至少一个解码器，对从奇偶校验电路输出的n位显示数据进行解码; 多个锁存电路，锁存由解码器解码的数据; 以及多个数据线驱动器部分，其基于由锁存电路锁存的数据驱动显示面板的数据线。

公开(公告)号：US06473059B1

公开(公告)日：2002-10-29

申请号：US09619471

申请日：2000-07-19

申请人： Tadashi Yasue

发明人： Tadashi Yasue

IPC分类号： G09G500

CPC分类号： G09G3/3611 ,  G06F3/147 ,  G09G3/3622 ,  G09G5/39 ,  G09G2310/0278 ,  G09G2360/18 ,  G09G2370/08 ,  Y10T307/653

摘要： A display driver IC which adopts a serial transmission system to reduce the number of terminal pins, transmits a command and data efficiently and also can speed-up data transmission. The display driver IC comprises an interface circuit to which signals from an external MPU are input, a command decoder for decoding command data input from the external MPU through the interface circuit, a storage section in which display data input from the external MPU through the interface circuit is written; and a display driving section for driving a display on the basis of the display data written in the storage section. The interface circuit comprises a first input terminal to which a serial data input signal is input, a second input terminal to which a serial clock signal is input and a third input terminal to which a chip select signal is input. The serial data input signal uses, as a unit data column, 9 bits including data groups of 8 bits which the external MPU simultaneously processes and identification data D/C of one bit which identifies whether the data groups are groups of the command data or the display data.

摘要翻译： 一种显示驱动器IC，采用串行传输系统来减少终端引脚数量，有效传输命令和数据，并可加速数据传输。 显示驱动器IC包括输入来自外部MPU的信号的接口电路，用于通过接口电路解码从外部MPU输入的命令数据的命令解码器，其中通过接口从外部MPU输入的显示数据的存储部 电路写入; 以及显示驱动部分，用于根据写在存储部分中的显示数据来驱动显示器。 接口电路包括输入串行数据输入信号的第一输入端子，输入串行时钟信号的第二输入端子和输入芯片选择信号的第三输入端子。 串行数据输入信号使用包括外部MPU同时处理的8位数据组的9位和识别数据组是指令数据组的一位的识别数据D / C的9位， 显示数据。

公开(公告)号：US06459330B2

公开(公告)日：2002-10-01

申请号：US09768776

申请日：2001-01-23

申请人： Tadashi Yasue

发明人： Tadashi Yasue

IPC分类号： G05F110

CPC分类号： H02M3/07

摘要： A DC-DC voltage boosting method is capable of reducing power consumption by detecting a margin of a boosting voltage, even if the display mode of a liquid crystal panel or a displayed content changes. Included are the steps of (a) boosting an input voltage by using clock signals to generate a boosted voltage, (b) generating a stabilized operating voltage by using the boosted voltage, (c) detecting a margin voltage between the boosted voltage and the operating voltage, and (d) based on the detected result in step (c), adjusting the frequency of the clock signals used in step (a) or fixing at least one of the clock signals which control switching components.

摘要翻译： 即使液晶面板的显示模式或显示的内容发生变化，DC-DC升压方式也能够通过检测升压电压的余量来降低功耗。 包括以下步骤：（a）通过使用时钟信号来提高输入电压以产生升高的电压，（b）通过使用升压电压产生稳定的工作电压，（c）检测升压电压和操作之间的裕度电压 电压和（d）基于步骤（c）中的检测结果，调整步骤（a）中使用的时钟信号的频率或固定控制开关组件的时钟信号中的至少一个。