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    MEMORY ACCESS DEVICE FOR MEMORY SHARING AMONG PLURALITY OF PROCESSORS, AND ACCESS METHOD FOR SAME
    1.
    发明申请
    MEMORY ACCESS DEVICE FOR MEMORY SHARING AMONG PLURALITY OF PROCESSORS, AND ACCESS METHOD FOR SAME 有权
    用于处理器多重存储器共享的存储器访问设备及其访问方法

    公开(公告)号：US20140059286A1

    公开(公告)日：2014-02-27

    申请号：US13989743

    申请日：2011-10-06

    申请人： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

    发明人： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

    IPC分类号： G06F13/16

    CPC分类号： G11C7/1048 ,  G06F13/1642 ,  G06F13/1647 ,  G06F13/1663 ,  G06F13/4234 ,  G11C7/1072

    摘要： Provided is a memory access device for a shared memory mechanism of main memory for a plurality of CPUs. The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

    摘要翻译： 提供了一种用于多个CPU的主存储器的共享存储器机构的存储器访问装置。 本发明包括使用存储器作为主存储器的多个CPU，使用存储器作为缓冲器的另一功能块，控制从多个CPU到存储器的访问传输的CPU接口，以及用于执行访问转移的仲裁的DRAM控制器 记忆。 其中，CPU接口使得来自多个CPU的访问请求等待，并且接收并存储每个访问的地址，数据传输模式和数据大小，向DRAM控制器通知访问请求，然后在接收到 访问请求根据授权信号向DRAM控制器发送信息，于是DRAM控制器接收授权信号，并且基于访问仲裁，指定已经被授权传输的CPU，以便将授权信号发送到 CPU接口。

    Holding by a memory controller multiple central processing unit memory access requests, and performing the multiple central processing unit memory requests in one transfer cycle
    2.
    发明授权
    Holding by a memory controller multiple central processing unit memory access requests, and performing the multiple central processing unit memory requests in one transfer cycle 有权
    由存储器控制器控制多个中央处理单元存储器访问请求，并且在一个传送周期中执行多个中央处理单元存储器请求

    公开(公告)号：US09268721B2

    公开(公告)日：2016-02-23

    申请号：US13989743

    申请日：2011-10-06

    申请人： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

    发明人： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

    IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F13/16

    CPC分类号： G11C7/1048 ,  G06F13/1642 ,  G06F13/1647 ,  G06F13/1663 ,  G06F13/4234 ,  G11C7/1072

    摘要： The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

    摘要翻译： 本发明包括使用存储器作为主存储器的多个CPU，使用存储器作为缓冲器的另一功能块，控制从多个CPU到存储器的访问传输的CPU接口，以及用于执行访问转移的仲裁的DRAM控制器 记忆。 其中，CPU接口使得来自多个CPU的访问请求等待，并且接收并存储每个访问的地址，数据传输模式和数据大小，向DRAM控制器通知访问请求，然后在接收到 访问请求根据授权信号向DRAM控制器发送信息，于是DRAM控制器接收授权信号，并且基于访问仲裁，指定已经被授权传输的CPU，以便将授权信号发送到 CPU接口。

    EQUALIZING BANDWIDTH FOR MULTIPLE REQUESTERS USING A SHARED MEMORY SYSTEM
    3.
    发明申请
    EQUALIZING BANDWIDTH FOR MULTIPLE REQUESTERS USING A SHARED MEMORY SYSTEM 有权
    使用共享存储器系统对多个请求进行均衡带宽

    公开(公告)号：US20130179645A1

    公开(公告)日：2013-07-11

    申请号：US13344941

    申请日：2012-01-06

    申请人： Hisato Matsuo ,  Rika Nagahara ,  Scott J. Schaffer

    发明人： Hisato Matsuo ,  Rika Nagahara ,  Scott J. Schaffer

    IPC分类号： G06F12/00

    CPC分类号： G06F9/544 ,  G06F12/00 ,  G06F15/167

    摘要： A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed.

    摘要翻译： 公开了一种使用共享存储器系统来均衡使用者带宽的方法。 在一个实施例中，这种方法包括接收访问共享存储器系统的多个访问请求。 每个访问请求源自耦合到共享存储器系统的不同请求者。 该方法然后确定哪个访问请求已经等待最长时间访问共享存储器系统。 然后对访问请求进行排序，使得等待最长的访问请求在其他访问请求之后被传送到共享存储器系统。 与最长等待的访问请求相关联的请求者然后可以在发送最长等待的访问请求之后立即向附加存储器系统发送附加访问请求。 还公开了相应的装置和计算机程序产品。

    Equalizing bandwidth for multiple requesters using a shared memory system
    4.
    发明授权
    Equalizing bandwidth for multiple requesters using a shared memory system 有权
    使用共享内存系统为多个请求者均衡带宽

    公开(公告)号：US09208002B2

    公开(公告)日：2015-12-08

    申请号：US13344941

    申请日：2012-01-06

    申请人： Hisato Matsuo ,  Rika Nagahara ,  Scott Jeffrey Schaffer

    发明人： Hisato Matsuo ,  Rika Nagahara ,  Scott Jeffrey Schaffer

    IPC分类号： G06F12/00 ,  G06F9/54 ,  G06F15/167

    CPC分类号： G06F9/544 ,  G06F12/00 ,  G06F15/167

    摘要： A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed.

    摘要翻译： 公开了一种使用共享存储器系统来均衡使用者带宽的方法。 在一个实施例中，这种方法包括接收访问共享存储器系统的多个访问请求。 每个访问请求源自耦合到共享存储器系统的不同请求者。 该方法然后确定哪个访问请求已经等待最长时间访问共享存储器系统。 然后对访问请求进行排序，使得等待最长的访问请求在其他访问请求之后被传送到共享存储器系统。 与最长等待的访问请求相关联的请求者然后可以在发送最长等待的访问请求之后立即向附加存储器系统发送附加访问请求。 还公开了相应的装置和计算机程序产品。

    Decoding encoded data containing integrated data and header protection
    6.
    发明授权
    Decoding encoded data containing integrated data and header protection 失效
    对包含集成数据和头部保护的编码数据进行解码

    公开(公告)号：US08762805B2

    公开(公告)日：2014-06-24

    申请号：US12957651

    申请日：2010-12-01

    申请人： Roy Daron Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J Seger ,  Keisuke Tanaka

    发明人： Roy Daron Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J Seger ,  Keisuke Tanaka

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1012 ,  H03M13/1515 ,  H03M13/2909

    摘要： A method for decoding encoded data comprising integrated data and header protection is disclosed herein. In one embodiment, such a method includes receiving an extended data array. The extended data array includes a data array organized into rows and columns, headers appended to the rows of the data array, column ECC parity protecting the columns of the data array, and row ECC parity protecting the rows and headers combined. The method then decodes the extended data array. Among other operations, this decoding step includes checking the header associated with each row to determine whether the header is legal. If the header is legal, the method determines the contribution of the header to the corresponding row ECC parity. The method then reverses the contribution of the header to the corresponding row ECC parity. A corresponding apparatus (i.e., a tape drive configured to implement the above-described method) is also disclosed herein.

    摘要翻译： 本文公开了一种用于对包括集成数据和报头保护的编码数据进行解码的方法。 在一个实施例中，这种方法包括接收扩展数据阵列。 扩展数据阵列包括组织成行和列的数据阵列，附加到数据阵列行的标题，保护数据阵列列的ECC ECC奇偶校验和保护行和头组合的行ECC奇偶校验。 该方法然后解码扩展数据数组。 在其他操作中，该解码步骤包括检查与每行关联的标题以确定标题是否合法。 如果标题是合法的，则该方法确定标题对相应行ECC奇偶校验的贡献。 该方法然后将标题的贡献反转到对应的行ECC奇偶校验。 本文还公开了相应的装置（即，被配置为实现上述方法的磁带驱动器）。

    DECODING ENCODED DATA CONTAINING INTEGRATED DATA AND HEADER PROTECTION
    8.
    发明申请
    DECODING ENCODED DATA CONTAINING INTEGRATED DATA AND HEADER PROTECTION 失效
    解码包含一体化数据和编码保护的编码数据

    公开(公告)号：US20120144271A1

    公开(公告)日：2012-06-07

    申请号：US12957651

    申请日：2010-12-01

    申请人： Roy D. Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J. Seger ,  Keisuke Tanaka

    发明人： Roy D. Cideciyan ,  Hisato Matsuo ,  Thomas Mittelholzer ,  Kenji Ohtani ,  Paul J. Seger ,  Keisuke Tanaka

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1012 ,  H03M13/1515 ,  H03M13/2909

    摘要： A method for decoding encoded data comprising integrated data and header protection is disclosed herein. In one embodiment, such a method includes receiving an extended data array. The extended data array includes a data array organized into rows and columns, headers appended to the rows of the data array, column ECC parity protecting the columns of the data array, and row ECC parity protecting the rows and headers combined. The method then decodes the extended data array. Among other operations, this decoding step includes checking the header associated with each row to determine whether the header is legal. If the header is legal, the method determines the contribution of the header to the corresponding row ECC parity. The method then reverses the contribution of the header to the corresponding row ECC parity. A corresponding apparatus (i.e., a tape drive configured to implement the above-described method) is also disclosed herein.

    摘要翻译： 本文公开了一种用于对包括集成数据和报头保护的编码数据进行解码的方法。 在一个实施例中，这种方法包括接收扩展数据阵列。 扩展数据阵列包括组织成行和列的数据阵列，附加到数据阵列行的标题，保护数据阵列列的ECC ECC奇偶校验和保护行和头组合的行ECC奇偶校验。 该方法然后解码扩展数据数组。 在其他操作中，该解码步骤包括检查与每行关联的标题以确定标题是否合法。 如果标题是合法的，则该方法确定标题对相应行ECC奇偶校验的贡献。 该方法然后将标题的贡献反转到对应的行ECC奇偶校验。 本文还公开了相应的装置（即，被配置为实现上述方法的磁带驱动器）。