公开(公告)号：US20170351156A1

公开(公告)日：2017-12-07

申请号：US15538020

申请日：2015-05-29

Applicant: Hitachi, Ltd.

Inventor： Ryo IMAI ,  Hiroyuki MINEMURA

IPC: G02F1/35 ,  G02B5/18 ,  B23K26/55 ,  B23K26/00 ,  G02B6/13 ,  B23K26/06 ,  B23K103/00

CPC classification number: G02F1/3523 ,  B23K26/0006 ,  B23K26/0604 ,  B23K26/0608 ,  B23K26/53 ,  B23K26/55 ,  B23K2103/54 ,  G02B3/12 ,  G02B5/1857 ,  G02B6/13 ,  G02B19/0014 ,  G02B19/0023 ,  G02B19/0047

Abstract: An object of the present invention is to provide a technique capable of easily manufacturing a desired optical device at the inside of a transparent board. An optical device according to the present invention is manufactured by denaturing the vicinity of a hollow structure at the inside of the transparent board and deforming the shape of the hollow structure

公开(公告)号：US20160078932A1

公开(公告)日：2016-03-17

申请号：US14783846

申请日：2013-05-20

Applicant: HITACHI, LTD.

Inventor： Yoshitaka SASAGO ,  Hiroyuki MINEMURA ,  Kenzo KUROTSUCHI ,  Seiji MIURA ,  Satoru HANZAWA

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233

Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).

Abstract translation: 本发明的目的是提供一种半导体存储器件，其能够通过在大电流通过存储器链的同时抑制电压降并行执行读取操作并且通过减少数字来减小芯片面积来增加读取传送速率 的外围电路供电。 根据本发明的半导体存储器件包括平板形状的上电极和下电极，分别在第一和第二方向上延伸的第一和第二选择晶体管，以及布置在第一选择晶体管和第二选择晶体管之间的布线， 通过关闭第一选择晶体管（参见图2），下电极被配置为彼此电绝缘。