公开(公告)号：US20230116118A1

公开(公告)日：2023-04-13

申请号：US17795970

申请日：2021-01-28

申请人： Hitachi Energy Switzerland AG

发明人： Juergen Schuderer ,  Slavo Kicin ,  Fabian Mohn ,  Gernot Riedel

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00

摘要： A power semiconductor module includes a semiconductor board and a number of semiconductor chips attached to the semiconductor board. Each semiconductor chip has two power electrodes. An adapter board is attached to the semiconductor board above the semiconductor chips. The adapter board includes a terminal area for each semiconductor chip on a side facing away from the semiconductor board. The adapter board, in each terminal area, provides a power terminal for each power electrode of the semiconductor chip associated with the terminal area. Each power terminal is electrically connected via a respective vertical post below the terminal area with a respective semiconductor chip and each of the power terminals has at least two plug connectors. Jumper connectors interconnect the plug connectors for electrically connecting power electrodes of different semiconductor chips.

公开(公告)号：US20220399279A1

公开(公告)日：2022-12-15

申请号：US17806337

申请日：2022-06-10

申请人： Hitachi Energy Switzerland AG

发明人： Slavo Kicin ,  Arne Schroeder ,  Farhad Yaghoubi

IPC分类号： H01L23/538 ,  H01L23/64 ,  H01L25/07

摘要： A power semiconductor module includes a plurality of semiconductor switches arranged in a plurality of groups. Each semiconductor switch has a first terminal and a second terminal having a controlled path therebetween and a control terminal. A plurality of first group contacts are each connected to the first terminals of the semiconductor switches of a respective group and a plurality of second group contacts are each connected to the second terminals of the semiconductor switches of the respective group. A plurality of control group contacts are each connected to the control terminals of the semiconductor switches of the respective group. An interconnection bridge connects the control group contacts and the first group contacts of the plurality of groups. The interconnection bridge has a layer structure with a first conductive layer and a second conductive layer being separated by an insulating layer.

公开(公告)号：US11742312B2

公开(公告)日：2023-08-29

申请号：US17311562

申请日：2019-10-17

申请人： Hitachi Energy Switzerland AG

发明人： Didier Cottet ,  Slavo Kicin

IPC分类号： H01L23/00

CPC分类号： H01L24/72 ,  H01L2224/72 ,  H01L2924/01013 ,  H01L2924/01042 ,  H01L2924/1033 ,  H01L2924/10272

摘要： A power semiconductor module comprises abase plate (1); a semiconductor chip (2) disposed on and in contact with a top surface of the base plate (1), a preform (3) disposed on and in contact with a top surface of the semiconductor chip (2); and a pressing element (4) in contact with and applying a pressure onto a top surface of the preform (3). The preform (3) comprises a first electrically conductive layer (6) and a second electrically conductive layer (5). The first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining a recess (9) in the first electrically conductive layer (6) of the preform (3), wherein the recess (9) may annularly surround the protrusion (7). The at least one protrusion (7) is made from the same material as the first electrically conducting layer (6) and integrally formed with it or the first electrically conducting layer (6) and the at least one protrusion (7) are made from different materials. At least a portion of the second electrically conductive layer (5) is positioned in the recess (9) and on the top surface of the semiconductor chip (2). The material of the at least one protrusion (7) has a higher melting point than the material of the second electrically conductive layer (5). The power semiconductor module is configured so that in an event of semiconductor chip failure with heat dissipation, the protrusion (7) of the first electrically conductive layer (6) penetrates through residual material (8) of the semiconductor chip (2) upon pressure applied by the pressing element (4) towards the base plate (1) so as to establish a contact between the protrusion (7) of the first electrically conductive layer (6) and the base plate (1) and form a short circuit bridging the defective semiconductor chip (2) in a short circuit failure mode. The bottom surface of the preform (3) may be formed by a bottom surface of the second electrically conductive layer (5) alone or by a bottom surface of the second electrically conductive layer (5) and a bottom surface of the protrusion (7).

公开(公告)号：US20230112582A1

公开(公告)日：2023-04-13

申请号：US17913662

申请日：2021-02-25

申请人： Hitachi Energy Switzerland AG

发明人： Slavo Kicin ,  Chunlei Liu ,  Andrey Petrov ,  Gernot Riedel

IPC分类号： H01L23/495 ,  H01L23/373 ,  H01L21/50

摘要： In one embodiment, a power module device includes a base plate, an electrically insulating ceramic layer on the base plate, and an electrically insulating first insulating layer on the ceramic layer. The first insulating layer includes a prepreg material. An electrically conductive lead frame is disposed on the first insulating layer and electrically insulated therefrom. A power semiconductor device disposed on the lead frame and embedded between the lead frame and a second insulating layer.

公开(公告)号：US20220238493A1

公开(公告)日：2022-07-28

申请号：US17611305

申请日：2020-04-02

申请人： Hitachi Energy Switzerland AG

发明人： Arne Schroeder ,  Slavo Kicin ,  Fabian Mohn ,  Juergen Schuderer

IPC分类号： H01L25/07 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00

摘要： A power semiconductor module includes a main substrate and power semiconductor chips. Each power semiconductor chip is bonded to the main conductive layer with the first power electrode. A first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes. The module also includes a first insulation layer and a first conductive layer overlying the first insulation layer as well as a second insulation layer and a second conductive layer overlying the second insulation layer. The first conductive layer provides a first gate conductor area and a first auxiliary emitter conductor area for the first group. The second conductive layer provides a second gate conductor area and a second auxiliary emitter conductor area for the second group.