利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.014 秒)

    Power Semiconductor Module with Laser-Welded Leadframe
    1.
    发明申请
    Power Semiconductor Module with Laser-Welded Leadframe 有权

    公开(公告)号：US20220406745A1

    公开(公告)日：2022-12-22

    申请号：US17604717

    申请日：2020-03-12

    申请人： Hitachi Energy Switzerland AG

    发明人： Niko Pavlicek ,  Fabian Mohn ,  Markus Thut ,  Swen Koenig

    IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/07

    摘要： A power semiconductor module includes a substrate with a structured metallization layer and a number of semiconductor chips. Each chip has a first power electrode bonded to the metallization layer. A leadframe is laser-welded to second power electrodes of the semiconductor chips for electrically interconnecting the semiconductor chips. A control conductor is attached to the leadframe opposite to the semiconductor chips and is electrically isolated from the leadframe. The control conductor is electrically connected to control electrodes of the semiconductor chips in the group.

    Power Semiconductor Module with Low Inductance Gate Crossing
    2.
    发明申请
    Power Semiconductor Module with Low Inductance Gate Crossing 有权

    公开(公告)号：US20220238493A1

    公开(公告)日：2022-07-28

    申请号：US17611305

    申请日：2020-04-02

    申请人： Hitachi Energy Switzerland AG

    发明人： Arne Schroeder ,  Slavo Kicin ,  Fabian Mohn ,  Juergen Schuderer

    IPC分类号： H01L25/07 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00

    摘要： A power semiconductor module includes a main substrate and power semiconductor chips. Each power semiconductor chip is bonded to the main conductive layer with the first power electrode. A first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes. The module also includes a first insulation layer and a first conductive layer overlying the first insulation layer as well as a second insulation layer and a second conductive layer overlying the second insulation layer. The first conductive layer provides a first gate conductor area and a first auxiliary emitter conductor area for the first group. The second conductive layer provides a second gate conductor area and a second auxiliary emitter conductor area for the second group.

    Power semiconductor package with highly reliable chip topside
    3.
    发明授权
    Power semiconductor package with highly reliable chip topside 有权

    公开(公告)号：US11538734B2

    公开(公告)日：2022-12-27

    申请号：US17046620

    申请日：2019-04-08

    申请人： Hitachi Energy Switzerland AG

    发明人： Fabian Mohn ,  Alexey Sokolov ,  Chunlei Liu

    IPC分类号： H01L23/373 ,  H01L21/48 ,  H01L23/00

    摘要： A power semiconductor module includes a substrate with a metallization layer and a power semiconductor chip bonded to the metallization layer of the substrate. A metallic plate has a first surface bonded to a surface of the power semiconductor chip opposite to the substrate. The metallic plate has a central part and a border that are both bonded to the power semiconductor chip. The border of the metallic plate is structured in such a way that the metallic plate has less metal material per volume at the border as compared to the central part of the metallic plate. Metallic interconnection elements are bonded to a second surface of the metallic plate at the central part.

    Free Configurable Power Semiconductor Module
    6.
    发明申请
    Free Configurable Power Semiconductor Module 有权

    公开(公告)号：US20230116118A1

    公开(公告)日：2023-04-13

    申请号：US17795970

    申请日：2021-01-28

    申请人： Hitachi Energy Switzerland AG

    发明人： Juergen Schuderer ,  Slavo Kicin ,  Fabian Mohn ,  Gernot Riedel

    IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00

    摘要： A power semiconductor module includes a semiconductor board and a number of semiconductor chips attached to the semiconductor board. Each semiconductor chip has two power electrodes. An adapter board is attached to the semiconductor board above the semiconductor chips. The adapter board includes a terminal area for each semiconductor chip on a side facing away from the semiconductor board. The adapter board, in each terminal area, provides a power terminal for each power electrode of the semiconductor chip associated with the terminal area. Each power terminal is electrically connected via a respective vertical post below the terminal area with a respective semiconductor chip and each of the power terminals has at least two plug connectors. Jumper connectors interconnect the plug connectors for electrically connecting power electrodes of different semiconductor chips.

    Arrangement of a Power Semiconductor Module and a Cooler
    9.
    发明申请
    Arrangement of a Power Semiconductor Module and a Cooler 有权

    公开(公告)号：US20220254653A1

    公开(公告)日：2022-08-11

    申请号：US17630080

    申请日：2020-07-24

    申请人： Hitachi Energy Switzerland AG

    发明人： Daniele Torresin ,  Fabian Mohn ,  Bruno Agostini ,  Thomas Gradinger ,  Juergen Schuderer

    IPC分类号： H01L21/48 ,  H01L23/473 ,  H01L23/367

    摘要： In one embodiment a power semiconductor module includes a substrate having a first substrate side for carrying an electric circuit and having a second substrate side being located opposite to the first substrate side. The second substrate side has a flat surface and is adapted for coming in contact with a cooler. A cooling area that is surrounded by a connecting area is located at the second substrate side. A first casing component of the cooler is connected to the second substrate side at the connecting area and a second casing component is connected to the first casing component such that a cooling channel for providing the cooling area with cooling fluid is provided between the first casing component and the second casing component. A cooling structure can be welded to the cooling area at the second substrate side.