公开(公告)号：US07315997B2

公开(公告)日：2008-01-01

申请号：US10846517

申请日：2004-05-17

申请人： Hitoshi Watanabe ,  Hideaki Konishi ,  Yuko Katoh ,  Kazuyuki Yamamura ,  Naoko Karasawa ,  Takeshi Doi ,  Osamu Ōkano ,  Junko Kumagai ,  Koichi Itaya ,  Daisuke Tsukuda ,  Ryuji Shimizu ,  Toshihito Shimizu

发明人： Hitoshi Watanabe ,  Hideaki Konishi ,  Yuko Katoh ,  Kazuyuki Yamamura ,  Naoko Karasawa ,  Takeshi Doi ,  Osamu Ōkano ,  Junko Kumagai ,  Koichi Itaya ,  Daisuke Tsukuda ,  Ryuji Shimizu ,  Toshihito Shimizu

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/31724 ,  G01R31/318555 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.

摘要翻译： 设计支持装置包括：输入通过使用除了测试电路之外的硬宏小区创建的用户网络列表的单元，以及使用硬宏小区来排列硬宏小区的单元，硬宏小区（其中定时收敛的物理信息包括测试终端） 并且测试电路被嵌入作为布置/布线信息。 此外，包括使用嵌入到框架中的测试电路的布置/布线信息来布置和布线测试电路的单元，识别布置/布线信息的单元，其中测试电路的布置/布线信息从布置/ 通过布线获得的布线信息，单元输出逻辑结构的网表。

公开(公告)号：US20050172254A1

公开(公告)日：2005-08-04

申请号：US10846517

申请日：2004-05-17

申请人： Hitoshi Watanabe ,  Hideaki Konishi ,  Yuko Katoh ,  Kazuyuki Yamamura ,  Naoko Karasawa ,  Takeshi Doi ,  Osamu Okano ,  Junko Kumagai ,  Koichi Itaya ,  Daisuke Tsukuda ,  Ryuji Shimizu ,  Toshihito Shimizu

发明人： Hitoshi Watanabe ,  Hideaki Konishi ,  Yuko Katoh ,  Kazuyuki Yamamura ,  Naoko Karasawa ,  Takeshi Doi ,  Osamu Okano ,  Junko Kumagai ,  Koichi Itaya ,  Daisuke Tsukuda ,  Ryuji Shimizu ,  Toshihito Shimizu

IPC分类号： G06F17/50 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/82

CPC分类号： G06F17/5045 ,  G01R31/31724 ,  G01R31/318555 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.

摘要翻译： 设计支持装置包括：输入通过使用除了测试电路之外的硬宏小区创建的用户网络列表的单元，以及使用硬宏小区来排列硬宏小区的单元，硬宏小区（其中定时收敛的物理信息包括测试终端） 并且测试电路被嵌入作为布置/布线信息。 此外，包括使用嵌入到框架中的测试电路的布置/布线信息来布置和布线测试电路的单元，识别布置/布线信息的单元，其中测试电路的布置/布线信息从布置/ 通过布线获得的布线信息，单元输出逻辑结构的网表。

公开(公告)号：US20070168816A1

公开(公告)日：2007-07-19

申请号：US11647363

申请日：2006-12-29

申请人： Takahisa Hiraide ,  Hitoshi Yamanaka ,  Junko Kumagai ,  Hideaki Konishi ,  Daisuke Maruyama

发明人： Takahisa Hiraide ,  Hitoshi Yamanaka ,  Junko Kumagai ,  Hideaki Konishi ,  Daisuke Maruyama

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/31813 ,  G01R31/318547 ,  G06F2201/83

摘要： An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

公开(公告)号：US07178078B2

公开(公告)日：2007-02-13

申请号：US10000089

申请日：2001-12-04

申请人： Takahisa Hiraide ,  Hitoshi Yamanaka ,  Junko Kumagai ,  Hideaki Konishi ,  Daisuke Maruyama

发明人： Takahisa Hiraide ,  Hitoshi Yamanaka ,  Junko Kumagai ,  Hideaki Konishi ,  Daisuke Maruyama

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/31813 ,  G01R31/318547 ,  G06F2201/83

摘要： An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

摘要翻译： 一种设备能够在短时间内进行高质量测试，而不会对设计人员造成严重的设计限制，而无需昂贵的测试仪。 该装置包括内置在集成电路中的图形发生器，以产生伪随机图案作为测试图案。 多个移位寄存器在所述集成电路内配置有顺序电路元件。 自动测试模式生成单元生成ATPG模式。 模式修改器基于所述ATPG模式修改在由所述模式生成器生成的所述伪随机模式中需要设置预定值以便检测故障的部分，并且输入所述修改的伪随机模式 到移位寄存器。