公开(公告)号：US20070168816A1

公开(公告)日：2007-07-19

申请号：US11647363

申请日：2006-12-29

申请人： Takahisa Hiraide ,  Hitoshi Yamanaka ,  Junko Kumagai ,  Hideaki Konishi ,  Daisuke Maruyama

发明人： Takahisa Hiraide ,  Hitoshi Yamanaka ,  Junko Kumagai ,  Hideaki Konishi ,  Daisuke Maruyama

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/31813 ,  G01R31/318547 ,  G06F2201/83

摘要： An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

公开(公告)号：US07178078B2

公开(公告)日：2007-02-13

申请号：US10000089

申请日：2001-12-04

申请人： Takahisa Hiraide ,  Hitoshi Yamanaka ,  Junko Kumagai ,  Hideaki Konishi ,  Daisuke Maruyama

发明人： Takahisa Hiraide ,  Hitoshi Yamanaka ,  Junko Kumagai ,  Hideaki Konishi ,  Daisuke Maruyama

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/31813 ,  G01R31/318547 ,  G06F2201/83

摘要： An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

摘要翻译： 一种设备能够在短时间内进行高质量测试，而不会对设计人员造成严重的设计限制，而无需昂贵的测试仪。 该装置包括内置在集成电路中的图形发生器，以产生伪随机图案作为测试图案。 多个移位寄存器在所述集成电路内配置有顺序电路元件。 自动测试模式生成单元生成ATPG模式。 模式修改器基于所述ATPG模式修改在由所述模式生成器生成的所述伪随机模式中需要设置预定值以便检测故障的部分，并且输入所述修改的伪随机模式 到移位寄存器。

公开(公告)号：US07734973B2

公开(公告)日：2010-06-08

申请号：US11647363

申请日：2006-12-29

申请人： Takahisa Hiraide ,  Hitoshi Yamanaka

发明人： Takahisa Hiraide ,  Hitoshi Yamanaka

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/31813 ,  G01R31/318547 ,  G06F2201/83

摘要： An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

摘要翻译： 一种设备能够在短时间内进行高质量测试，而不会对设计人员造成严重的设计限制，而无需昂贵的测试仪。 该装置包括内置在集成电路中的图形发生器，以产生伪随机图案作为测试图案。 多个移位寄存器在所述集成电路内配置有顺序电路元件。 自动测试模式生成单元生成ATPG模式。 模式修改器基于所述ATPG模式修改在由所述模式生成器生成的所述伪随机模式中需要设置预定值以便检测故障的部分，并且输入所述修改的伪随机模式 到移位寄存器。

公开(公告)号：US07353440B2

公开(公告)日：2008-04-01

申请号：US10967280

申请日：2004-10-19

申请人： Akihiko Ohwada ,  Tatsumi Nakada ,  Hitoshi Yamanaka

发明人： Akihiko Ohwada ,  Tatsumi Nakada ,  Hitoshi Yamanaka

IPC分类号： G01R31/28

CPC分类号： G06F11/263 ,  G01R31/318547 ,  G06F11/267

摘要： In processors having multiple cores, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block, which makes it possible to perform LSI tests more efficiently. A processor includes a plurality of logic block circuits, which include at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits. The processor further includes, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.

摘要翻译： 在具有多个核的处理器（例如CMP）中，为每个逻辑块提供独立的MISR测试图案压缩电路，这使得可以更有效地执行LSI测试。 处理器包括多个逻辑块电路，其包括至少第一处理器核心电路和第二处理器核心电路，每个处理器核心电路具有扫描链电路并且可独立操作;以及公共块电路，具有扫描链电路 以及由第一处理器核心电路和第二处理器核心电路共享的高速缓存电路。 处理器还包括针对每个逻辑块的测试图形生成电路，其可操作以产生测试图案并将测试图案输入到每个逻辑块电路的扫描链，以及测试图案压缩电路，其可操作以接受作为输入并压缩 由每个逻辑块电路的扫描链输出的测试模式。

公开(公告)号：US08356217B2

公开(公告)日：2013-01-15

申请号：US12786760

申请日：2010-05-25

申请人： Hitoshi Yamanaka ,  Masahiro Yanagida

发明人： Hitoshi Yamanaka ,  Masahiro Yanagida

IPC分类号： G01R31/28 ,  H03K3/289

CPC分类号： G01R31/318533 ,  G01R31/318544

摘要： A storage circuit, an integrated circuit and a scanning method are provided. The storage circuit includes a first storage element, and a second storage element connected to an output of the first storage element. The storage circuit includes a first setting circuit that is configured to set data of a first logic value to the first storage element when a clear signal is applied, and a second setting circuit that is configured to set data of a second logic value to the second storage element and transmit the second logic value data to a different storage circuit when a second clock signal is in an off state and the clear signal is applied.

摘要翻译： 提供存储电路，集成电路和扫描方法。 存储电路包括第一存储元件和连接到第一存储元件的输出的第二存储元件。 存储电路包括第一设置电路，其被配置为当施加清除信号时将第一逻辑值的数据设置为第一存储元件;以及第二设置电路，被配置为将第二逻辑值的数据设置为第二逻辑值 存储元件，并且当第二时钟信号处于关闭状态并且施加清除信号时，将第二逻辑值数据传送到不同的存储电路。

公开(公告)号：US20050240850A1

公开(公告)日：2005-10-27

申请号：US10967280

申请日：2004-10-19

申请人： Akihiko Ohwada ,  Tatsumi Nakada ,  Hitoshi Yamanaka

发明人： Akihiko Ohwada ,  Tatsumi Nakada ,  Hitoshi Yamanaka

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F9/26 ,  G06F9/34 ,  G06F11/00 ,  G06F11/22 ,  G06F11/263 ,  G06F11/267 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/08 ,  G06F12/10 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/28 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F11/263 ,  G01R31/318547 ,  G06F11/267

摘要： In processors having a multicore, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block in a multicore processor such as a CMP comprising a plurality of processor cores makes it possible to perform LSI tests more efficiently. A processor comprises a plurality of logic block circuits, plurality of logic block circuits comprising at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits, the processor further comprising, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.

摘要翻译： 在具有多核（诸如CMP）的处理器中，为包括多个处理器核心的多核处理器（例如CMP）中的每个逻辑块提供独立的MISR测试图案压缩电路，使得可以更有效地执行LSI测试。 处理器包括多个逻辑块电路，多个逻辑块电路至少包括第一处理器核心电路和第二处理器核心电路，每个处理器核心电路具有扫描链电路并且可独立操作;以及公共块电路，其具有 扫描链电路和由第一处理器核心电路和第二处理器核心电路共享的高速缓存电路，处理器还包括针对每个逻辑块的测试图形生成电路，其可操作以产生测试图案并输入测试图案 到每个逻辑块电路的扫描链，以及测试图案压缩电路，其可操作以接受作为输入并压缩由每个逻辑块电路的扫描链输出的测试图案。