公开(公告)号：US20070288821A1

公开(公告)日：2007-12-13

申请号：US11797347

申请日：2007-05-02

申请人： Tatsuru Matsuo ,  Takahisa Hiraide

发明人： Tatsuru Matsuo ,  Takahisa Hiraide

IPC分类号： G01R31/311

CPC分类号： G01R31/318547

摘要： A semiconductor integrated circuit includes plural shift registers that receive plural test patterns randomly generated, respectively, a mask device that masks, among the shift registers, a target shift register specified by a mask pattern randomly generated. When a shift register other than the target shift register outputs an unknown value, the mask device masks the shift register according to a control signal. When the target shift register outputs a fault value, the mask device releases a mask of the target shift register according to a control signal.

摘要翻译： 半导体集成电路包括多个移位寄存器，分别接收随机生成的多个测试图形，掩模装置在移位寄存器中屏蔽由随机生成的掩模图案指定的目标移位寄存器。 当除目标移位寄存器之外的移位寄存器输出未知值时，掩码器件根据控制信号屏蔽移位寄存器。 当目标移位寄存器输出故障值时，掩模装置根据控制信号释放目标移位寄存器的掩码。

公开(公告)号：US20070245197A1

公开(公告)日：2007-10-18

申请号：US11521173

申请日：2006-09-14

申请人： Takahisa Hiraide

发明人： Takahisa Hiraide

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318357 ,  G01R31/318328

摘要： A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate path that extends, via the segment, from an upstream circuit element to a downstream circuit element; a judging unit that judges whether length of the candidate path is longer than a predetermined length; and a determining unit that determines whether to determine the candidate path as a target path to be subjected to a fault simulation based on a result of judgment.

摘要翻译： 故障分析装置包括：提取单元，从目标电路中的多个路径提取包括故障点的段; 检测单元，其检测经由所述段从上游电路元件延伸到下游电路元件的候选路径; 判断单元，其判断候选路径的长度是否长于预定长度; 以及确定单元，其基于判断结果来确定是否将候选路径确定为要进行故障模拟的目标路径。

公开(公告)号：US5815513A

公开(公告)日：1998-09-29

申请号：US821728

申请日：1997-03-20

申请人： Takahisa Hiraide

发明人： Takahisa Hiraide

IPC分类号： G06F11/22 ,  G01R31/3183 ,  G06F17/50 ,  G01R31/28 ,  G06F3/00 ,  G06F11/00 ,  G06G7/48

CPC分类号： G01R31/318307

摘要： A test pattern preparation system for testing an LSI circuit, the system includes: a circuit data file for storing various circuit data; an old test pattern file for storing old test patterns; a test pattern preparation unit for performing a logic simulation, detecting "simultaneous-change action" based on a result of the logic simulation, and preparing a new test pattern in accordance with the circuit data and the old test patterns; and a new test pattern file for storing new test patterns which are prepared by the test pattern preparation unit.

摘要翻译： 一种用于测试LSI电路的测试模式准备系统，该系统包括：用于存储各种电路数据的电路数据文件; 用于存储旧测试模式的旧测试模式文件; 用于执行逻辑模拟的测试模式准备单元，基于逻辑模拟的结果检测“同步变化动作”，并根据电路数据和旧的测试模式准备新的测试模式; 以及用于存储由测试图案准备单元准备的新测试图案的新测试图案文件。

公开(公告)号：US07734973B2

公开(公告)日：2010-06-08

申请号：US11647363

申请日：2006-12-29

申请人： Takahisa Hiraide ,  Hitoshi Yamanaka

发明人： Takahisa Hiraide ,  Hitoshi Yamanaka

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/31813 ,  G01R31/318547 ,  G06F2201/83

摘要： An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

摘要翻译： 一种设备能够在短时间内进行高质量测试，而不会对设计人员造成严重的设计限制，而无需昂贵的测试仪。 该装置包括内置在集成电路中的图形发生器，以产生伪随机图案作为测试图案。 多个移位寄存器在所述集成电路内配置有顺序电路元件。 自动测试模式生成单元生成ATPG模式。 模式修改器基于所述ATPG模式修改在由所述模式生成器生成的所述伪随机模式中需要设置预定值以便检测故障的部分，并且输入所述修改的伪随机模式 到移位寄存器。

公开(公告)号：US08644093B2

公开(公告)日：2014-02-04

申请号：US13465096

申请日：2012-05-07

申请人： Takahisa Hiraide

发明人： Takahisa Hiraide

IPC分类号： G11C7/06 ,  G11C7/22 ,  G11C17/00

CPC分类号： G11C17/16 ,  G11C29/785

摘要： A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch.

摘要翻译： 写入电路包括用于存储要写入OTP宏的写入数据的存储器; 控制器，用于应用导致OTP宏执行写入数据写入的第一信号，并且应用使得OTP宏执行读取OTP宏存储的数据的第二信号; 以及比较器，用于将存储在存储器中的数据响应于第二信号从OTP宏读取的数据进行比较，并输出比较结果，其中如果比较结果指示匹配，则控制器结束与写入数据相关联的处理， 并且如果比较结果指示不匹配，则再次施加第一和第二信号。

公开(公告)号：US20130039114A1

公开(公告)日：2013-02-14

申请号：US13465096

申请日：2012-05-07

申请人： Takahisa HIRAIDE

发明人： Takahisa HIRAIDE

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C29/785

摘要： A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch.

摘要翻译： 写入电路包括用于存储要写入OTP宏的写入数据的存储器; 控制器，用于应用导致OTP宏执行写入数据写入的第一信号，并且应用使得OTP宏执行读取OTP宏存储的数据的第二信号; 以及比较器，用于将存储在存储器中的数据响应于第二信号从OTP宏读取的数据进行比较，并输出比较结果，其中如果比较结果指示匹配，则控制器结束与写入数据相关联的处理， 并且如果比较结果指示不匹配，则再次施加第一和第二信号。

公开(公告)号：US07895492B2

公开(公告)日：2011-02-22

申请号：US12073553

申请日：2008-03-06

申请人： Takahisa Hiraide ,  Tatsuru Matsuo

发明人： Takahisa Hiraide ,  Tatsuru Matsuo

IPC分类号： G06F11/263 ,  G06F11/30

CPC分类号： G01R31/318538 ,  G01R31/318541 ,  G06F7/584 ,  G06F2207/583

摘要： In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log24 is also formed in the LFSR. As a result, a smaller clock count is required for the LFSR to output a test pattern that matches a test pattern automatically generated by an ATPG.

摘要翻译： 在线性反馈移位寄存器（LFSR）中，形成主要使用F / F的四位移位寄存器，并且还提供将第一位和最后位的异或反馈到第一位的异或电路，由此 输出具有最大周期为15的测试图案。在LFSR中还形成了可以基于具有最大时钟数4和平均时钟数log 24的控制信号的输入来执行测试模式的任意相位变化的相变电路 。 因此，LFSR需要较小的时钟计数，以输出与ATPG自动生成的测试模式相匹配的测试模式。

公开(公告)号：US07757138B2

公开(公告)日：2010-07-13

申请号：US11797347

申请日：2007-05-02

申请人： Tatsuru Matsuo ,  Takahisa Hiraide

发明人： Tatsuru Matsuo ,  Takahisa Hiraide

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A semiconductor integrated circuit includes plural shift registers that receive plural test patterns randomly generated, respectively, a mask device that masks, among the shift registers, a target shift register specified by a mask pattern randomly generated. When a shift register other than the target shift register outputs an unknown value, the mask device masks the shift register according to a control signal. When the target shift register outputs a fault value, the mask device releases a mask of the target shift register according to a control signal.

摘要翻译： 半导体集成电路包括多个移位寄存器，分别接收随机生成的多个测试图形，掩模装置在移位寄存器中屏蔽由随机生成的掩模图案指定的目标移位寄存器。 当除目标移位寄存器之外的移位寄存器输出未知值时，掩码器件根据控制信号屏蔽移位寄存器。 当目标移位寄存器输出故障值时，掩模装置根据控制信号释放目标移位寄存器的掩码。

公开(公告)号：US20050149804A1

公开(公告)日：2005-07-07

申请号：US11023457

申请日：2004-12-29

申请人： Takahisa Hiraide

发明人： Takahisa Hiraide

IPC分类号： G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G06F11/00

CPC分类号： G01R31/31813 ,  G01R31/31835 ,  G01R31/318385

摘要： The present invention provides an integrated circuit test device and method which creates a pattern for minimizing a difference from a pattern generated by a pattern generation device. In the invention, a list of all failures assumed to be in the circuit is created, and, for example, a random number pattern is inputted so that a signal value in the circuit is defined by a logic simulation using the inputted pattern, as a result of which the controllability, observability and testability are calculated. A target failure minimizing the testability is selected from the list, for which target failure path-sensitization is performed using the controllability and observability of the input pattern, which pattern is corrected so as to minimize the number of inversions of signal values of the input pattern. A failure simulation for the target failure is also performed using the corrected pattern, and when a failure to be detected further exists, the failure is removed from the failure list.

摘要翻译： 本发明提供了一种集成电路测试装置和方法，该集成电路测试装置和方法产生用于最小化与图案生成装置生成的图案的差异的图案。 在本发明中，创建了假设在电路中的所有故障的列表，并且例如输入随机数模式，使得通过使用输入模式的逻辑模拟来定义电路中的信号值，作为 其结果是计算可控性，可观察性和可测试性。 从列表中选择最小化可测试性的目标故障，使用输入模式的可控性和可观察性来执行目标故障路径敏化，该模式被校正，以便最小化输入模式的信号值的反转次数 。 目标故障的故障模拟也使用校正模式进行，当进一步存在检测失败时，故障从故障列表中移除。

公开(公告)号：US08166380B2

公开(公告)日：2012-04-24

申请号：US11521173

申请日：2006-09-14

申请人： Takahisa Hiraide

发明人： Takahisa Hiraide

IPC分类号： G06F11/00 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00

CPC分类号： G01R31/318357 ,  G01R31/318328

摘要： A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate path that extends, via the segment, from an upstream circuit element to a downstream circuit element; a judging unit that judges whether length of the candidate path is longer than a predetermined length; and a determining unit that determines whether to determine the candidate path as a target path to be subjected to a fault simulation based on a result of judgment.

摘要翻译： 故障分析装置包括：提取单元，从目标电路中的多个路径提取包括故障点的段; 检测单元，其检测经由所述段从上游电路元件延伸到下游电路元件的候选路径; 判断单元，其判断候选路径的长度是否长于预定长度; 以及确定单元，其基于判断结果来确定是否将候选路径确定为要进行故障模拟的目标路径。