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公开(公告)号：US5155699A
公开(公告)日：1992-10-13
申请号：US550503
申请日：1990-07-10
申请人： Ho-sun Chung , Sin-jin Kim , Tae-hun Kim
发明人： Ho-sun Chung , Sin-jin Kim , Tae-hun Kim
CPC分类号： G06F7/535 , G06F2207/4802 , G06F2207/5353
摘要： A divider using neural network configurations comprises a subtractor, a selecting means, a first latch means, a second latch means, a shift register and a control means. The subtractor of the divider comprises plural inverters and plural 3-bit full-adders which are composed of four output lines, an input synapse group, a first bias synapse group, a second bias synapse group, a feedback synapse group, a neuron group and an inverter group.
摘要翻译： 使用神经网络配置的分频器包括减法器，选择装置，第一锁存装置，第二锁存装置，移位寄存器和控制装置。 除法器的减法器包括多个反相器和多个3位全加器，它们由四条输出线，输入突触组，第一偏压突触组，第二偏压突触组，反馈突触组，神经元组和 逆变器组。
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2.发明授权Divider circuit adopting a neural network architecture to increase division processing speed and reduce hardware components 失效分频电路采用神经网络架构，增加分割处理速度，减少硬件组件
公开(公告)号：US5130944A
公开(公告)日：1992-07-14
申请号：US549942
申请日：1990-07-09
申请人： Ho-sun Chung , Sin-jin Kim , Tae-hun Kim
发明人： Ho-sun Chung , Sin-jin Kim , Tae-hun Kim
CPC分类号： G06F7/535 , G06N3/063 , G06F2207/4802 , G06F2207/5353
摘要： A divider circuit for efficiently and quickly performing a hardware implemented division by adopting a neural network architecture. The circuit includes a series of cascaded subtracter components that complement the divisor input and effectively perform an adder function. The subtracters include a synaptic configuration consisting of PMOS transistors, NMOS transistors, and CMOS inverters. The components are arranged in accordance with the predetermined connection strength assigned to each of the transistors and its respective position in the neural type network arrangement.
摘要翻译： 一种用于通过采用神经网络架构来有效且快速地执行硬件实现的划分的分频器电路。 该电路包括一系列级联减法器组件，用于补偿除数输入并有效执行加法器功能。 减法器包括由PMOS晶体管，NMOS晶体管和CMOS反相器组成的突触配置。 根据分配给每个晶体管的预定连接强度及其在神经型网络布置中的相应位置来布置组件。
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公开(公告)号：US5293458A
公开(公告)日：1994-03-08
申请号：US745348
申请日：1991-08-15
申请人： Ho-sun Chung , Sin-jin Kim
发明人： Ho-sun Chung , Sin-jin Kim
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/063 , G06N99/00 , G11C11/54 , H01L21/822 , H01L27/04
CPC分类号： G06N3/063
摘要： Disclosed is a multi-layer neural network and circuit design method. The multi-layer neural network receiving an m-bit input and generating an n-bit output comprises a neuron having a cascaded pair of CMOS inverters and having an output node of the preceding CMOS inverter among the pair of CMOS inverters as its inverted output node and an output node of the succeeding CMOS inverter as its non-inverted output node, an input layer having m neurons to receive the m-bit input, an output layer having n neurons to generate the n-bit output, at least one hidden layer provided with n neurons to transfer the input received from the input layer to the directly upper hidden layer or the output layer, an input synapse group in a matrix having each predetermined weight value to connect each output of neurons on the input layer to each neuron of the output layer and at least one hidden layer, at least one transfer synapse group in a matrix having each predetermined weight value to connect each output of neurons of the hidden layer to each neuron of its directly upper hidden layer or of the output layer, and a bias synapse group for biasing each input node of neurons of the hidden layers and the output layer.
摘要翻译： 公开了一种多层神经网络和电路设计方法。 接收m位输入并生成n位输出的多层神经网络包括具有级联的CMOS反相器对的神经元，并且在一对CMOS反相器之间具有前述CMOS反相器的输出节点作为其反相输出节点 以及后续CMOS反相器的输出节点作为其非反相输出节点，具有m个神经元以接收m位输入的输入层，具有n个神经元以产生n位输出的输出层，至少一个隐藏层 提供有n个神经元以将从输入层接收的输入传送到直接上隐藏层或输出层，矩阵中的输入突触组具有每个预定权重值，以将输入层上的神经元的每个输出连接到每个神经元 输出层和至少一个隐藏层，具有每个预定权重值的矩阵中的至少一个转移突触组，以将隐层的神经元的每个输出连接到其直接上层的每个神经元 隐层或输出层，以及偏置突触组，用于偏置隐层和输出层的神经元的每个输入节点。
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公开(公告)号：US5448682A
公开(公告)日：1995-09-05
申请号：US373479
申请日：1995-01-17
申请人： Ho-sun Chung , Kyung-hun Lee
发明人： Ho-sun Chung , Kyung-hun Lee
CPC分类号： G06N3/063
摘要： A programmable multilayer neural network includes a weight storing circuit for storing the weight of each synapse to perform an intended function, an interfacing circuit for transmitting the weight value stored in the storing circuit to each synapse, and a multilayer neural network circuit programmed to have the weight from the weight storing circuit and for outputting an intended output.
摘要翻译： 可编程多层神经网络包括用于存储每个突触的重量以执行预期功能的权重存储电路，用于将存储在存储电路中的权重值发送到每个突触的接口电路，以及被编程为具有 并且用于输出预期的输出。
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5.发明授权
公开(公告)号：US5177746A
公开(公告)日：1993-01-05
申请号：US550054
申请日：1990-07-09
申请人： Ho-sun Chung
发明人： Ho-sun Chung
摘要： An error correction circuit is provided which uses NMOS and PMOS synapses to form neural network type responses to a coded multi-bit input. Use of MOS technology logic in error correction circuits allows such devices to be easily interfaced with other like technology circuits without the need to use distinct interface logic as with conventional error correction circuitry.
摘要翻译： 提供了一种使用NMOS和PMOS突触形成对编码的多位输入的神经网络类型响应的纠错电路。 在纠错电路中使用MOS技术逻辑允许这样的设备容易地与其他类似的技术电路接口，而不需要像传统的纠错电路那样使用不同的接口逻辑。
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公开(公告)号：US5745655A
公开(公告)日：1998-04-28
申请号：US375473
申请日：1995-01-19
申请人： Ho-sun Chung , Ik-soo Lee
发明人： Ho-sun Chung , Ik-soo Lee
CPC分类号： G06N3/0635
摘要： A mapping circuit includes a linear circuit for outputting a signal which is linearly changed with respect to its input, a non-linear circuit for outputting a signal which is non-linearly changed with respect to its input, and an adder for summing the output signals of the linear and non-linear circuits and an external input signal. A chaotic neuron circuit using the mapping circuit has a simple structure and more precise chaos characteristics. A chaotic neural network can thus be formed by the serial and/or parallel interconnection of a plurality of chaotic neuron circuits, wherein the weight of each neuron is controlled.
摘要翻译： 映射电路包括用于输出相对于其输入线性改变的信号的线性电路，用于输出相对于其输入非线性改变的信号的非线性电路，以及用于对输出信号求和的加法器 的线性和非线性电路以及外部输入信号。 使用映射电路的混沌神经元电路具有简单的结构和更精确的混沌特性。 因此，可以通过多个混沌神经元电路的串联和/或并联互连形成混沌神经网络，其中每个神经元的权重被控制。
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公开(公告)号：US5442209A
公开(公告)日：1995-08-15
申请号：US253215
申请日：1994-06-02
申请人： Ho-sun Chung
发明人： Ho-sun Chung
CPC分类号： G06N3/063 , H01L29/7831
摘要： A synapse MOS transistor has gate electrodes of different lengths, different widths or different lengths and widths, between one source region and one drain region. Thus, when using the synapse MOS transistor to implement a neural network, the chip area can be greatly reduced.
摘要翻译： 突触MOS晶体管具有在一个源极区域和一个漏极区域之间具有不同长度，不同宽度或不同长度和宽度的栅电极。 因此，当使用突触MOS晶体管来实现神经网络时，芯片面积可以大大降低。
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公开(公告)号：US5613042A
公开(公告)日：1997-03-18
申请号：US379211
申请日：1995-01-27
申请人： Ho-sun Chung , Hye-young Tak
发明人： Ho-sun Chung , Hye-young Tak
CPC分类号： G06N3/0418
摘要： A chaotic recurrent neural network includes N chaotic neural networks for receiving an external input and the outputs of N-1 chaotic neural networks among said N chaotic neural networks and performing an operation according to the following dynamic equation ##EQU1## wherein W.sub.ij is a synapse connection coefficient of the feedback input from the "j"th neuron to the "i"th neuron, X.sub.i (t) is the output of the "i"th neuron at time t, and .gamma..sub.i, .alpha. and and k are a time-delaying constant, a non-negative parameter and a refractory time attenuation constant, respectively, and wherein Z.sub.i (t) represents X.sub.i (t) when i belongs to the neuron group I and represents a.sub.i (t) when i belongs to the external input group E. Also, a learning algorithm for the chaotic recurrent neural network increases its learning efficiency.
摘要翻译： 混沌循环神经网络包括N个混沌神经网络，用于接收所述N个混沌神经网络中的N-1混沌神经网络的外部输入和N-1混沌神经网络的输出，并根据以下动态方程（IMAGE）执行操作，其中Wij是突触连接 从“j”个神经元到“i”个神经元的反馈输入的系数，Xi（t）是在时间t的“i”个神经元的输出，γi，α和k是时间 - 延迟常数，非负参数和难治时间衰减常数，其中当i属于神经元组I时，Zi（t）表示Xi（t），并且当i属于外部输入组时表示ai（t） 另外，混沌循环神经网络的学习算法提高了学习效率。
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公开(公告)号：US5517139A
公开(公告)日：1996-05-14
申请号：US381514
申请日：1995-02-01
申请人： Ho-sun Chung , Yil-suk Yang
发明人： Ho-sun Chung , Yil-suk Yang
CPC分类号： G06N3/0635
摘要： A non-linear circuit includes a first variable resistor one end of which is applied with an input signal, an amplifier whose inverting input is connected to the other end of the first variable resistor and whose non-inverting input is connected to ground, a second variable resistor one end of which is connected to the inverting input of the amplifier, a third variable resistor one end of which is connected to the output of the amplifier and the other end being connected to the other end of the second variable resistor, and a fourth variable resistor one end of which is applied with the input signal and the other end being connected to the third variable resistor. A chaotic neuron circuit using the non-linear circuit includes a first sample-and-hold circuit for sampling the input signal in response to a first clock signal, a non-linear circuit for generating an output signal having a non-linear characteristic with respect to the output of the first sample-and-hold circuit, an adder for summing the output signal of the non-linear circuit and an external input signal, a second sample-and-hold circuit for sampling the output of the adder in response to a second clock signal and for outputting the result to the input of the first sample-and-hold circuit, and a clock generator for generating the first and second clock signals. The non-linear circuit and the chaotic neuron circuit using the same have a simple constitution.
摘要翻译： 非线性电路包括其一端被施加有输入信号的第一可变电阻器，其反相输入端连接到第一可变电阻器的另一端并且其非反相输入端连接到地的放大器，第二可变电阻器 可变电阻器的一端连接到放大器的反相输入端，第三可变电阻器的一端连接到放大器的输出端，另一端连接到第二可变电阻器的另一端， 第四可变电阻器的一端施加有输入信号，另一端连接到第三可变电阻器。 使用非线性电路的混沌神经元电路包括用于响应于第一时钟信号对输入信号进行采样的第一采样和保持电路，用于产生具有非线性特性的输出信号的非线性电路 到第一采样保持电路的输出，用于对非线性电路的输出信号和外部输入信号求和的加法器，用于响应于第二取样和保持电路对加法器的输出进行采样的第二采样和保持电路 第二时钟信号，用于将结果输出到第一采样保持电路的输入;以及时钟发生器，用于产生第一和第二时钟信号。 非线性电路和使用该非线性电路的混沌神经元电路具有简单的结构。
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公开(公告)号：US5260706A
公开(公告)日：1993-11-09
申请号：US864190
申请日：1992-04-03
申请人： Ho-sun Chung
发明人： Ho-sun Chung
摘要： A priority encoder using a MOS array and neural network concepts is composed of an input side neuron group, an output side neuron group, a synapse group, a bias group and inverters. The encoder is simple in its construction and fast in its operating speed compared with the conventional priority encoders utilizing simple Boolean logic.
摘要翻译： 使用MOS阵列和神经网络概念的优先编码器由输入侧神经元组，输出侧神经元组，突触组，偏置组和逆变器组成。 与使用简单布尔逻辑的常规优先编码器相比，编码器结构简单，运行速度快。
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