GATEWAY OFFERING LOGICAL MODEL MAPPED TO INDEPENDENT UNDERLYING NETWORKS
    1.
    发明申请
    GATEWAY OFFERING LOGICAL MODEL MAPPED TO INDEPENDENT UNDERLYING NETWORKS 有权
    网关提供逻辑模型映射到独立的基础网络

    公开(公告)号:US20150316923A1

    公开(公告)日:2015-11-05

    申请号:US14269903

    申请日:2014-05-05

    Abstract: An apparatus includes a first interface configured to communicate over a first industrial process control network using a first protocol. The apparatus also includes a second interface configured to communicate over a second industrial process control network using a second protocol. The apparatus further includes a third interface configured to communicate with at least one supervisory device over a third network. In addition, the apparatus includes at least one processing device configured to provide concurrent access for the at least one supervisory device to process control devices coupled to the first and second industrial process control networks during a migration of process control devices that use the first protocol to process control devices that use the second protocol.

    Abstract translation: 一种装置包括被配置为使用第一协议通过第一工业过程控制网络进行通信的第一接口。 该装置还包括被配置为使用第二协议通过第二工业过程控制网络进行通信的第二接口。 该装置还包括配置成通过第三网络与至少一个监控装置通信的第三接口。 另外,该设备包括至少一个处理设备,该处理设备被配置为为至少一个监控设备提供并发访问,以便在使用第一协议的过程控制设备的迁移期间处理耦合到第一和第二工业过程控制网络的控制设备 使用第二协议的过程控制设备。

    Detecting path faults in parallel redundancy protocol communications

    公开(公告)号:US11265208B1

    公开(公告)日:2022-03-01

    申请号:US17137035

    申请日:2020-12-29

    Abstract: An electronic device and other electronic device include a first and second port that utilizes a parallel redundancy protocol in a communications network including a first and second lane. The devices include a processing circuit, a PRP handler, a protocol stack, a memory, permanent storage accessible by the processing circuit, and transmit and receive circuitry for transmitting and receiving packets. A redundancy manager is for identifying path faults in the network. The processing circuit implements a method of detecting network path fault, including the other electronic device transmitting a frame pair over the first lane and second lane. The electronic device receives the frame pair and implements a receive processing flow, when the first frame or the second frame is identified to be a redundant frame, removes the redundant frame, and compares a first frame parameter to a second frame parameter to determine when the path fault is present.

Patent Agency Ranking