公开(公告)号：US20110037109A1

公开(公告)日：2011-02-17

申请号：US12910552

申请日：2010-10-22

申请人： Hong-Gun KIM ,  Ju-Seon GOO ,  Mun-Jun KIM ,  Yong-Soon CHOI ,  Sung-Tae KIM ,  Eun-Kyung BAEK

发明人： Hong-Gun KIM ,  Ju-Seon GOO ,  Mun-Jun KIM ,  Yong-Soon CHOI ,  Sung-Tae KIM ,  Eun-Kyung BAEK

IPC分类号： H01L29/68

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.

摘要翻译： 在一些实施例中，半导体衬底包括限定有源区的沟槽。 半导体器件还包括设置在沟槽中的下部和上部器件隔离图案。 栅极绝缘图案和控制栅电极设置在半导体衬底上以跨越有源区。 电荷存储电极位于控制栅电极和有源区之间。 栅极绝缘图案位于电荷存储电极和有源区之间，并且栅间绝缘图案直接接触有源区之间的上部器件隔离图案。

公开(公告)号：US20080035984A1

公开(公告)日：2008-02-14

申请号：US11618155

申请日：2006-12-29

申请人： Hong-Gun KIM ,  Ju-Seon GOO ,  Mun-Jun KIM ,  Yong-Soon CHOI ,  Sung-Tae KIM ,  Eun-Kyung BAEK

发明人： Hong-Gun KIM ,  Ju-Seon GOO ,  Mun-Jun KIM ,  Yong-Soon CHOI ,  Sung-Tae KIM ,  Eun-Kyung BAEK

IPC分类号： H01L29/788 ,  H01L21/762

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

摘要翻译： 制造闪速存储器件的方法的一个实施例包括在半导体衬底上形成沟槽掩模图案，其包括依次层叠的栅极绝缘图案和电荷存储图案; 使用沟槽掩模图案作为蚀刻掩模蚀刻半导体衬底，以形成限定有源区的沟槽; 并且顺序地形成沟槽中的下部和上部器件隔离图案。 在上部器件隔离图案上顺序地形成栅极间绝缘膜和控制栅极膜之后，形成控制栅极膜，栅极间绝缘图案和阴极管栅极图案，从而提供跨越有源区域的栅极线。

公开(公告)号：US20070098892A1

公开(公告)日：2007-05-03

申请号：US11468932

申请日：2006-08-31

申请人： Eun-Ae CHUNG ,  Kyoung-Ryul YOON ,  Ki-Vin IM ,  Jae-Hyun YEO ,  Sung-Tae KIM ,  Young-Sun KIM ,  Young-Geun PARK

发明人： Eun-Ae CHUNG ,  Kyoung-Ryul YOON ,  Ki-Vin IM ,  Jae-Hyun YEO ,  Sung-Tae KIM ,  Young-Sun KIM ,  Young-Geun PARK

IPC分类号： C23C16/00 ,  B05D3/02 ,  B05D5/12

CPC分类号： H01L21/022 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31641 ,  H01L28/55

摘要： In a method of forming a layer and a method of manufacturing a capacitor using the same, a preliminary zirconium oxide film is formed on a substrate by introducing a first reactant including a zirconium precursor, and a first oxidant onto the substrate. A thermal treatment is performed on the preliminary zirconium oxide film to form a first zirconium oxide film having a dense and crystalline structure. An aluminum oxide film is formed on the first zirconium oxide film by introducing a second reactant including an aluminum precursor, and a second oxidant onto the substrate. The thermally-treated layer including the first zirconium oxide film and the aluminum oxide film may form a dielectric layer of a capacitor.

摘要翻译： 在形成层的方法和使用其制造电容器的方法中，通过将包含锆前体和第一氧化剂的第一反应物引入到衬底上，在衬底上形成预氧化锆膜。 对预氧化锆膜进行热处理，以形成具有致密和结晶结构的第一氧化锆膜。 通过将包含铝前体和第二氧化剂的第二反应物引入到基底上，在第一氧化锆膜上形成氧化铝膜。 包含第一氧化锆膜和氧化铝膜的热处理层可以形成电容器的电介质层。

公开(公告)号：US20060181189A1

公开(公告)日：2006-08-17

申请号：US11276035

申请日：2006-02-10

申请人： Sung-Tae KIM

发明人： Sung-Tae KIM

IPC分类号： H01J1/14

CPC分类号： H05K3/361 ,  H01J11/10 ,  H01J11/46 ,  H05K1/117 ,  H05K3/323 ,  H05K2201/09427 ,  H05K2201/098

摘要： A plasma display apparatus comprising a connector is provided. The plasma display apparatus comprises a plasma display panel comprising an electrode of a predetermined width and a connector comprising an electrode line of a width narrower than the predetermined width of the electrode to supply a driving signal to the electrode. A distance between the electrode line and an adjacent electrode line is longer than a distance between the electrode and an adjacent electrode.

公开(公告)号：US20080061696A1

公开(公告)日：2008-03-13

申请号：US11939325

申请日：2007-11-13

申请人： Sung-Tae KIM

发明人： Sung-Tae KIM

IPC分类号： H01J17/49

CPC分类号： H05K3/361 ,  H01J11/10 ,  H01J11/46 ,  H05K1/117 ,  H05K3/323 ,  H05K2201/09427 ,  H05K2201/098

摘要： A plasma display apparatus comprising a connector is provided. The plasma display apparatus comprises a plasma display panel comprising an electrode of a predetermined width and a connector comprising an electrode line of a width narrower than the predetermined width of the electrode to supply a driving signal to the electrode. A distance between the electrode line and an adjacent electrode line is longer than a distance between the electrode and an adjacent electrode.

摘要翻译： 提供了包括连接器的等离子体显示装置。 等离子体显示装置包括等离子体显示面板，其包括预定宽度的电极和包括宽度比电极的预定宽度窄的电极线的连接器，以向电极提供驱动信号。 电极线和相邻电极线之间的距离比电极和相邻电极之间的距离长。