公开(公告)号：US20060125367A1

公开(公告)日：2006-06-15

申请号：US11283764

申请日：2005-11-22

申请人： Hongyeol Kim ,  Yungi Kim

发明人： Hongyeol Kim ,  Yungi Kim

IPC分类号： H01J17/49

CPC分类号： H01J11/12 ,  H01J11/36 ,  H01J2211/368

摘要： There is provided a plasma display panel, and more particularly, to a barrier rib structure of a plasma display panel. The plasma display panel comprises a main barrier rib formed on an effective surface of a panel to form a discharge cell; and an auxiliary barrier rib which protrudes in at least one of a horizontal direction or a vertical direction from the effective surface of the panel.

摘要翻译： 提供了等离子体显示面板，更具体地，涉及等离子体显示面板的障壁结构。 等离子体显示面板包括形成在面板的有效表面上以形成放电单元的主障壁; 以及辅助障壁，其从所述面板的有效表面沿水平方向或垂直方向中的至少一个突出。

公开(公告)号：US07569990B2

公开(公告)日：2009-08-04

申请号：US11283764

申请日：2005-11-22

申请人： Hongyeol Kim ,  Yungi Kim

发明人： Hongyeol Kim ,  Yungi Kim

IPC分类号： H01J17/49

CPC分类号： H01J11/12 ,  H01J11/36 ,  H01J2211/368

摘要： There is provided a plasma display panel, and more particularly, to a barrier rib structure of a plasma display panel. The plasma display panel comprises a main barrier rib formed on an effective surface of a panel to form a discharge cell; and an auxiliary barrier rib which protrudes in at least one of a horizontal direction or a vertical direction from the effective surface of the panel.

摘要翻译： 提供了等离子体显示面板，更具体地，涉及等离子体显示面板的障壁结构。 等离子体显示面板包括形成在面板的有效表面上以形成放电单元的主障壁; 以及辅助障壁，其从所述面板的有效表面沿水平方向或垂直方向中的至少一个突出。

公开(公告)号：US08558385B2

公开(公告)日：2013-10-15

申请号：US13200359

申请日：2011-09-23

申请人： Jaeman Yoon ,  Yungi Kim ,  Kangyoon Lee ,  Youngwoong Son

发明人： Jaeman Yoon ,  Yungi Kim ,  Kangyoon Lee ,  Youngwoong Son

IPC分类号： H01L23/48

CPC分类号： H01L21/76838 ,  H01L21/32139 ,  H01L21/743 ,  H01L23/522 ,  H01L27/0203 ,  H01L27/105 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d2 in the inner region, and d2′ in the intermediate region, where d2

摘要翻译： 一种互连结构，用于半导体器件（具有至少包括内部区域，至少包括内部区域的中间区域和至少位于与内部区域相对的中间区域的一侧的外部区域的区域） 包括：一对或多对第一和第二信号线，每对从内部区域延伸到中间区域;第一和第二信号线的第一部分和第二部分分别平行，第一部分位于 内部区域;至少第一信号线的第一和第二部分不是共线的;以及对于包括内部区域中的以下量值d2的每对的对内线间距d（i），以及d2' 在中间区域，其中d2

公开(公告)号：US20120013015A1

公开(公告)日：2012-01-19

申请号：US13200359

申请日：2011-09-23

申请人： Jaeman Yoon ,  Yungi Kim ,  Kangyoon Lee ,  Youngwoong Son

发明人： Jaeman Yoon ,  Yungi Kim ,  Kangyoon Lee ,  Youngwoong Son

IPC分类号： H01L23/48

CPC分类号： H01L21/76838 ,  H01L21/32139 ,  H01L21/743 ,  H01L23/522 ,  H01L27/0203 ,  H01L27/105 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d2 in the inner region, and d2′ in the intermediate region, where d2

摘要翻译： 一种互连结构，用于半导体器件（具有至少包括内部区域，至少包括内部区域的中间区域和至少位于与内部区域相对的中间区域的一侧的外部区域的区域） 包括：一对或多对第一和第二信号线，每对从内部区域延伸到中间区域;第一和第二信号线的第一部分和第二部分分别平行，第一部分位于 内部区域;至少第一信号线的第一和第二部分不是共线的;以及对于包括内部区域中的以下量值d2的每对的对内线间距d（i），以及d2' 在中间区域，其中d2

公开(公告)号：US08008155B2

公开(公告)日：2011-08-30

申请号：US11808462

申请日：2007-06-11

申请人： Jaeman Yoon ,  Yungi Kim ,  Hyeoungwon Seo ,  Kangyoon Lee

发明人： Jaeman Yoon ,  Yungi Kim ,  Hyeoungwon Seo ,  Kangyoon Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L29/0673 ,  H01L29/513

摘要： An electrode structure, e.g., a gate electrode for a transistor, includes: a volume of semiconductor material; a gate oxide on the semiconductor volume; a barrier layer, including silicon nitride, on the gate oxide layer; an adhesion layer on the barrier layer; and a metallic layer on the adhesion layer.

摘要翻译： 电极结构，例如晶体管的栅电极，包括：半导体材料的体积; 半导体体上的栅极氧化物; 在栅极氧化物层上的包括氮化硅的阻挡层; 阻挡层上的粘附层; 和粘合层上的金属层。

公开(公告)号：US08058169B2

公开(公告)日：2011-11-15

申请号：US11764660

申请日：2007-06-18

申请人： Jaeman Yoon ,  Yungi Kim ,  Kangyoon Lee ,  Youngwoong Son

发明人： Jaeman Yoon ,  Yungi Kim ,  Kangyoon Lee ,  Youngwoong Son

IPC分类号： H01L21/31

CPC分类号： H01L21/76838 ,  H01L21/32139 ,  H01L21/743 ,  H01L23/522 ,  H01L27/0203 ,  H01L27/105 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d2 in the inner region, and d2′ in the intermediate region, where d2

摘要翻译： 一种互连结构，用于半导体器件（具有至少包括内部区域，至少包括内部区域的中间区域和至少位于与内部区域相对的中间区域的一侧的外部区域的区域） 包括：一对或多对第一和第二信号线，每对从内部区域延伸到中间区域;第一和第二信号线的第一部分和第二部分分别平行，第一部分位于 内部区域;至少第一信号线的第一和第二部分不是共线的;以及对于包括内部区域中的以下量值d2的每对的对内线间距d（i），以及d2' 在中间区域，其中d2

公开(公告)号：US20080017997A1

公开(公告)日：2008-01-24

申请号：US11764660

申请日：2007-06-18

申请人： Jaeman Yoon ,  Yungi Kim ,  Kangyoon Lee ,  Youngwoong Son

发明人： Jaeman Yoon ,  Yungi Kim ,  Kangyoon Lee ,  Youngwoong Son

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/32139 ,  H01L21/743 ,  H01L23/522 ,  H01L27/0203 ,  H01L27/105 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d2 in the inner region, and d2′ in the intermediate region, where d2

摘要翻译： 一种互连结构，用于半导体器件（具有至少包括内部区域，至少包括内部区域的中间区域和至少位于与内部区域相对的中间区域的一侧的外部区域的区域） 包括：一对或多对第一和第二信号线，每对从内部区域延伸到中间区域;第一和第二信号线的第一部分和第二部分分别平行，第一部分位于 内部区域;至少第一信号线的第一和第二部分不共线;以及对于包括内部区域中的以下量值d 2的每对的对内线间距d（i），以及d 2'在中间区域，其中d 2

公开(公告)号：US20080017913A1

公开(公告)日：2008-01-24

申请号：US11808462

申请日：2007-06-11

申请人： Jaeman Yoon ,  Yungi Kim ,  Hyeoungwon Seo ,  Kangyoon Lee

发明人： Jaeman Yoon ,  Yungi Kim ,  Hyeoungwon Seo ,  Kangyoon Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L29/0673 ,  H01L29/513

摘要： An electrode structure, e.g., a gate electrode for a transistor, includes: a volume of semiconductor material; a gate oxide on the semiconductor volume; a barrier layer, including silicon nitride, on the gate oxide layer; an adhesion layer on the barrier layer; and a metallic layer on the adhesion layer.

摘要翻译： 电极结构，例如晶体管的栅电极，包括：半导体材料的体积; 半导体体上的栅极氧化物; 在栅极氧化物层上的包括氮化硅的阻挡层; 阻挡层上的粘附层; 和粘合层上的金属层。

公开(公告)号：US5308784A

公开(公告)日：1994-05-03

申请号：US955108

申请日：1992-10-01

申请人： Yungi Kim ,  Byeongyeol Kim ,  Soohan Choi

发明人： Yungi Kim ,  Byeongyeol Kim ,  Soohan Choi

IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L21/762

CPC分类号： H01L21/3086 ,  H01L21/76224 ,  Y10S148/05

摘要： There is disclosed in the present invention a method for manufacturing a semiconductor device including an isolation region defined by trenches having different or equal widths respectively on a single semiconductor substrate comprising the steps of:forming insulating films on the semiconductor substrate and then forming an aperture on a passive region (isolation region);forming spacers of etch rate different from that of the insulating films on sidewalls of the aperture to define ring-shaped trench regions surrounding outline of active regions;forming another insulating film of etch rate different from that of the spacers on the substrate where the spacers are defined and removing the spacers by etching to expose the substrate within the etched spacers; andforming trenches on the exposed area of the substrate, forming an insulating film of equal character to that of the insulating films used at the time of the formation of the aperture to refill the trenches and forming the spacers on the sidewalls of the insulating film in the passive region, thereby forming ring-shaped trenches surrounding the outlines of the active regions to be an isolation region.

摘要翻译： 在本发明中公开了一种用于制造半导体器件的方法，该半导体器件包括在单个半导体衬底上分别具有不同宽度或相等宽度的沟槽限定的隔离区域，包括以下步骤：在半导体衬底上形成绝缘膜，然后形成孔 被动区域（隔离区域）; 形成与孔的侧壁上的绝缘膜的蚀刻速率不同的间隔物，以限定围绕有源区的轮廓的环形沟槽区; 形成另一绝缘膜，该绝缘膜的蚀刻速率不同于限定衬垫的衬底上的间隔物的蚀刻速率，并通过蚀刻去除间隔物以暴露蚀刻间隔物内的衬底; 以及在衬底的暴露区域上形成沟槽，形成与在形成孔口时使用的绝缘膜的绝缘膜相同的绝缘膜，以重新填充沟槽并在绝缘膜的侧壁上形成间隔物 从而形成围绕有源区域的轮廓的环形沟槽成为隔离区域。