公开(公告)号：US07936588B2

公开(公告)日：2011-05-03

申请号：US12789691

申请日：2010-05-28

申请人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

发明人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C11/1673

摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。

公开(公告)号：US07755923B2

公开(公告)日：2010-07-13

申请号：US12212798

申请日：2008-09-18

申请人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

发明人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C11/1673

摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。

公开(公告)号：US20110194330A1

公开(公告)日：2011-08-11

申请号：US13088610

申请日：2011-04-18

申请人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

发明人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C11/1673

摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。

公开(公告)号：US20100232211A1

公开(公告)日：2010-09-16

申请号：US12789691

申请日：2010-05-28

申请人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

发明人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C11/1673

摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

公开(公告)号：US08098513B2

公开(公告)日：2012-01-17

申请号：US13088610

申请日：2011-04-18

申请人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

发明人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C11/1673

摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。

公开(公告)号：US20100067282A1

公开(公告)日：2010-03-18

申请号：US12212798

申请日：2008-09-18

申请人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

发明人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C7/22 ,  G11C11/14

CPC分类号： G11C7/14 ,  G11C11/1673

摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。

公开(公告)号：US08514605B2

公开(公告)日：2013-08-20

申请号：US13611225

申请日：2012-09-12

申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

IPC分类号： G11C5/08 ,  G11C27/00 ,  G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

公开(公告)号：US08296620B2

公开(公告)日：2012-10-23

申请号：US12198516

申请日：2008-08-26

申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

IPC分类号： G06F11/00

CPC分类号： G06F11/1048 ,  G11C2029/0411

摘要： A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.

摘要翻译： 一种使用至少一个数据块的方法，其中所述至少一个数据块包括用于存储数据的多个单元和至少一个误差标志位，所述方法包括：扫描所述数据块的错误; 确定数据块的错误率; 以及对所述至少一个数据块中的单元读取或写入的数据应用纠错码，其中，基于所述错误率应用所述纠错码，其中当所述错误率 低于错误阈值，并且当错误率处于或高于错误阈值时应用强纠错码。

公开(公告)号：US07830700B2

公开(公告)日：2010-11-09

申请号：US12269564

申请日：2008-11-12

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

IPC分类号： G11C11/00

CPC分类号： G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

摘要翻译： 本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。 第一组用户数据在第一PBA被写入所选择的块。 通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。 然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。

公开(公告)号：US20100188883A1

公开(公告)日：2010-07-29

申请号：US12360931

申请日：2009-01-28

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

IPC分类号： G11C11/56 ,  G11C11/00 ,  G11C7/00

CPC分类号： G11C8/06 ,  G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/44 ,  G11C29/76 ,  G11C2029/0411 ,  G11C2029/1208

摘要： Method and apparatus are disclosed for storing data to non-volatile resistive sense memory (RSM) memory cells of a semiconductor memory array, including but not limited to resistive random access memory (RRAM) and spin-torque transfer random access memory (STTRAM or STRAM) cells. In accordance with various embodiments, a plurality of addressable data blocks from a host device are stored in a buffer. At least a portion of each of the addressable data blocks are serially transferred to a separate register of a plurality of registers. The transferred portions of said addressable data blocks are thereafter simultaneously transferred from the registers to selected RSM cells of the array.

摘要翻译： 公开了用于将数据存储到半导体存储器阵列的非易失性电阻读出存储器（RSM）存储器单元的方法和装置，包括但不限于电阻随机存取存储器（RRAM）和自旋转矩传递随机存取存储器（STTRAM或STRAM ） 细胞。 根据各种实施例，来自主机设备的多个可寻址数据块被存储在缓冲器中。 每个可寻址数据块的至少一部分被串行地传送到多个寄存器的单独寄存器。 然后，所述可寻址数据块的传送部分从寄存器同时传送到阵列的所选RSM单元。