公开(公告)号：US5303196A

公开(公告)日：1994-04-12

申请号：US888226

申请日：1992-05-22

Applicant: Hoo D. Sang ,  Edmund J. Sprogis

Inventor： Hoo D. Sang ,  Edmund J. Sprogis

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC classification number: G11C7/18 ,  G11C11/4091 ,  G11C7/06

Abstract: An open bit line memory device and operational method are provided having performance characteristics commensurate with those of folded bit line architecture. The memory device includes a plurality of memory cells in open bit line configuration, at least some of which are interconnected by a bit line. A sense amplifier unit is coupled to the bit line for sensing a developing signal thereon during a predefined bit line signal development interval. The amplifier sets to one of two logical states during a subsequent setting interval. An electrical isolator is employed to decouple the bit line from the sense amplifier during the setting interval so that signal variations on the bit line do not effect the amplifier. Each bit line also has an associated reference voltage line, and the electrical isolator isolates both the bit line and the associated reference voltage line from the sense amplifier during amplifier's setting period.

Abstract translation: 提供了一种开放位线存储器件和操作方法，其具有与折叠位线架构相匹配的性能特征。 存储器件包括开放位线配置的多个存储器单元，其中至少一些由位线互连。 感测放大器单元耦合到位线，以在预定义的位线信号发展间隔期间感测其上的显影信号。 放大器在随后的设置间隔期间设置为两个逻辑状态之一。 采用电隔离器在设定间隔期间将位线与读出放大器去耦，使位线上的信号变化不影响放大器。 每个位线还具有相关联的参考电压线，并且电隔离器在放大器的设置周期期间将位线和相关联的参考电压线与读出放大器隔离。