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    Open bit line memory devices and operational method
    1.
    发明授权
    Open bit line memory devices and operational method 失效
    打开位线存储器件和操作方法

    公开(公告)号：US5303196A

    公开(公告)日：1994-04-12

    申请号：US888226

    申请日：1992-05-22

    Applicant: Hoo D. Sang ,  Edmund J. Sprogis

    Inventor： Hoo D. Sang ,  Edmund J. Sprogis

    IPC: G11C11/401 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

    CPC classification number: G11C7/18 ,  G11C11/4091 ,  G11C7/06

    Abstract: An open bit line memory device and operational method are provided having performance characteristics commensurate with those of folded bit line architecture. The memory device includes a plurality of memory cells in open bit line configuration, at least some of which are interconnected by a bit line. A sense amplifier unit is coupled to the bit line for sensing a developing signal thereon during a predefined bit line signal development interval. The amplifier sets to one of two logical states during a subsequent setting interval. An electrical isolator is employed to decouple the bit line from the sense amplifier during the setting interval so that signal variations on the bit line do not effect the amplifier. Each bit line also has an associated reference voltage line, and the electrical isolator isolates both the bit line and the associated reference voltage line from the sense amplifier during amplifier's setting period.

    Abstract translation: 提供了一种开放位线存储器件和操作方法，其具有与折叠位线架构相匹配的性能特征。 存储器件包括开放位线配置的多个存储器单元，其中至少一些由位线互连。 感测放大器单元耦合到位线，以在预定义的位线信号发展间隔期间感测其上的显影信号。 放大器在随后的设置间隔期间设置为两个逻辑状态之一。 采用电隔离器在设定间隔期间将位线与读出放大器去耦，使位线上的信号变化不影响放大器。 每个位线还具有相关联的参考电压线，并且电隔离器在放大器的设置周期期间将位线和相关联的参考电压线与读出放大器隔离。

    Coil inductor for on-chip or on-chip stack
    3.
    发明授权
    Coil inductor for on-chip or on-chip stack 有权
    用于片上或片上堆叠的线圈电感

    公开(公告)号：US09105627B2

    公开(公告)日：2015-08-11

    申请号：US13289071

    申请日：2011-11-04

    Applicant: Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    Inventor： Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    IPC: H01F5/00 ,  H01L27/08 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F17/00 ,  H01F41/00

    CPC classification number: H01L23/49822 ,  H01F17/0013 ,  H01F41/005 ,  H01F2017/0086 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

    Abstract: A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

    Abstract translation: 提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。 当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。 在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔， 通过硅通孔，在微电子或互连元件的厚度方向上延伸。 还提供了制造线圈电感器的方法。

    Through wafer vias with dishing correction methods
    7.
    发明授权
    Through wafer vias with dishing correction methods 有权
    通过具有凹陷校正方法的晶片通孔

    公开(公告)号：US08631570B2

    公开(公告)日：2014-01-21

    申请号：US13369414

    申请日：2012-02-09

    Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC: H01K3/10 ,  H05K3/02 ,  H05K3/10 ,  H01L29/40

    CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

    Abstract translation: 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

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