公开(公告)号：US08994571B1

公开(公告)日：2015-03-31

申请号：US13608832

申请日：2012-09-10

申请人： Hossein Zarei ,  Chieh-Yu Hsieh

发明人： Hossein Zarei ,  Chieh-Yu Hsieh

IPC分类号： H03M1/12

CPC分类号： H03M3/47 ,  H03M3/40

摘要： An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.

摘要翻译： 公开了一种模数转换器（ADC）和包括该ADC的接收器。 ADC包括被配置为接收接收机的I信号路径中的信号的第一滤波器和被配置为接收接收机的Q信号路径中的信号的第二滤波器。 ADC还包括与第一和第二滤波器交替地交替的量化器，以及与第一和第二滤波器交替地交替的至少一个DAC。 ADC中的开关被配置为在量化器的输入和第一和第二滤波器的输出之间交替连接，并且还被配置为在至少一个DAC的输出与第一和第二滤波器的输入之间交替连接。

公开(公告)号：US08264392B1

公开(公告)日：2012-09-11

申请号：US12963347

申请日：2010-12-08

申请人： Hossein Zarei ,  Chieh-Yu Hsieh

发明人： Hossein Zarei ,  Chieh-Yu Hsieh

IPC分类号： H03M1/12

CPC分类号： H03M3/47 ,  H03M3/40

摘要： An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.

摘要翻译： 公开了一种模数转换器（ADC）和包括该ADC的接收器。 ADC包括被配置为接收接收机的I信号路径中的信号的第一滤波器和被配置为接收接收机的Q信号路径中的信号的第二滤波器。 ADC还包括与第一和第二滤波器交替地交替的量化器，以及与第一和第二滤波器交替地交替的至少一个DAC。 ADC中的开关被配置为在量化器的输入和第一和第二滤波器的输出之间交替连接，并且还被配置为在至少一个DAC的输出与第一和第二滤波器的输入之间交替连接。

公开(公告)号：US20090279642A1

公开(公告)日：2009-11-12

申请号：US12118108

申请日：2008-05-09

申请人： Hossein Zarei

发明人： Hossein Zarei

IPC分类号： H04L27/22 ,  H03H11/16 ,  H03L7/06

CPC分类号： H03D7/165 ,  H03D3/006 ,  H03H11/28 ,  H03H11/32 ,  H03L7/08 ,  H03L7/0805 ,  H04L2027/0016

摘要： An integrated receiver circuit includes aphase locked loop circuit (21) with a voltage controlled oscillator (VCO) (25) and a quadrature generator circuit (29) which uses hybrid-branch line coupler circuits (27, 28) coupled to buffered VCO outputs, where the hybrid-branch line coupler circuits (27, 28) are tuned by same control voltage (25a) that controls the VCO (25). By replicating the VCO core circuitry in each hybrid-branch line coupler circuit (27, 28) under common control of a control voltage, calibrated quadrature signals are generated that have the same frequency as the phase locked loop circuit (21).

摘要翻译： 集成接收器电路包括具有压控振荡器（VCO）25的差分锁定环路电路21和使用耦合到缓冲VCO输出的混合分支线耦合器电路（27,28）的正交发生器电路（29） 其中混合分支线耦合器电路（27,28）由控制VCO（25）的相同控制电压（25a）调谐。 通过在控制电压的共同控制下复制每个混合支路线耦合器电路（27,28）中的VCO核心电路，生成与锁相环电路（21）具有相同频率的校准正交信号。

公开(公告)号：US09018996B1

公开(公告)日：2015-04-28

申请号：US12831186

申请日：2010-07-06

申请人： Hossein Zarei

发明人： Hossein Zarei

IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K3/00 ,  H03K5/13 ,  H03H11/16 ,  H04B1/7176

CPC分类号： H04B1/7176 ,  H03B27/00 ,  H03K5/15033

摘要： Circuits, architectures, a system and methods for providing quadrature output signals. The circuit generally includes a quadrature signal generator and a plurality of frequency dividers. The plurality of frequency dividers are each configured to receive a plurality of quadrature signal generator outputs at a first frequency and provide a plurality of outputs at a second frequency. The method generally includes providing a plurality of quadrature signals at a first frequency and dividing the first frequency of the quadrature signals by n, wherein n is an odd integer of at least 3, thereby providing a plurality of divided-by-n quadrature outputs at a second frequency, wherein the second frequency is about equal to the first frequency divided by n. The present disclosure further advantageously improves quadrature signal generation accuracy, reliability and/or performance.

摘要翻译： 电路，架构，提供正交输出信号的系统和方法。 电路通常包括正交信号发生器和多个分频器。 多个分频器被配置为以第一频率接收多个正交信号发生器输出，并以第二频率提供多个输出。 该方法通常包括以第一频率提供多个正交信号，并将正交信号的第一频率除以n，其中n是至少为3的奇整数，由此提供多个分频的正交输出 第二频率，其中第二频率大约等于除以n的第一频率。 本公开进一步有利地提高正交信号生成精度，可靠性和/或性能。

公开(公告)号：US08947067B1

公开(公告)日：2015-02-03

申请号：US13349218

申请日：2012-01-12

申请人： Hossein Zarei

发明人： Hossein Zarei

IPC分类号： G05F3/26

CPC分类号： G05F3/30

摘要： Disclosed is bandgap voltage reference generator having a programmable resistor. The programmable resistor can be programmed to provide a proper ratio between the PTAT current and the CTAT current to reduce the effect of process variations on the bandgap voltage. The bandgap voltage reference generator includes a calibration circuit that programs the programmable resistor.

摘要翻译： 公开了具有可编程电阻器的带隙电压基准发生器。 可编程电阻器可以编程为提供PTAT电流和CTAT电流之间的适当比例，以减少工艺变化对带隙电压的影响。 带隙电压参考发生器包括编程可编程电阻器的校准电路。

公开(公告)号：US08243855B2

公开(公告)日：2012-08-14

申请号：US12118108

申请日：2008-05-09

申请人： Hossein Zarei

发明人： Hossein Zarei

IPC分类号： H04L27/22

CPC分类号： H03D7/165 ,  H03D3/006 ,  H03H11/28 ,  H03H11/32 ,  H03L7/08 ,  H03L7/0805 ,  H04L2027/0016

摘要： An integrated receiver circuit includes a phase locked loop circuit (21) with a voltage controlled oscillator (VCO) (25) and a quadrature generator circuit (29) which uses hybrid-branch line coupler circuits (27, 28) coupled to buffered VCO outputs, where the hybrid-branch line coupler circuits (27, 28) are tuned by same control voltage (25a) that controls the VCO (25). By replicating the VCO core circuitry in each hybrid-branch line coupler circuit (27, 28) under common control of a control voltage, calibrated quadrature signals are generated that have the same frequency as the phase locked loop circuit (21).

摘要翻译： 集成接收器电路包括具有压控振荡器（VCO）（25）的锁相环电路（21）和使用耦合到缓冲VCO输出的混合分支线耦合器电路（27,28）的正交发生器电路（29） ，其中混合支路线耦合器电路（27,28）由控制VCO（25）的相同控制电压（25a）调谐。 通过在控制电压的共同控制下复制每个混合支路线耦合器电路（27,28）中的VCO核心电路，生成与锁相环电路（21）具有相同频率的校准正交信号。