公开(公告)号：US20070273631A1

公开(公告)日：2007-11-29

申请号：US11438230

申请日：2006-05-23

申请人： Hsiao-Lan Su ,  Pen-Hsin Chen ,  Yu-Jui Chang ,  Ying-Lieh Chen ,  Lin-Kai Bu

发明人： Hsiao-Lan Su ,  Pen-Hsin Chen ,  Yu-Jui Chang ,  Ying-Lieh Chen ,  Lin-Kai Bu

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3688 ,  G09G2330/06

摘要： An interface circuit for data transmission and the method thereof is described. The interface circuit includes a transmitter providing data through first data signals during the data periods corresponding to rising and falling edges of a clock signal, a transition detection unit selectively asserting a detection signal in response to the number of the first data signals having transitions between every two adjacent data periods, a transition reduction unit generating second data signals by outputting the inverted and non-inverted first data signals respectively when the detection signal is asserted and de-asserted, and a receiver restoring the data from the second data signals and the detection signal.

摘要翻译： 描述了用于数据传输的接口电路及其方法。 接口电路包括：在与时钟信号的上升沿和下降沿相对应的数据周期期间通过第一数据信号提供数据的发射器，转换检测单元响应于第一数据信号的数量响应于每个 两个相邻数据周期，转换缩减单元，当检测信号被断言和解除断言时分别输出反相和非反相第一数据信号，并且接收机从第二数据信号恢复数据和检测 信号。

公开(公告)号：US07821483B2

公开(公告)日：2010-10-26

申请号：US11438230

申请日：2006-05-23

申请人： Hsiao-Lan Su ,  Pen-Hsin Chen ,  Yu-Jui Chang ,  Ying-Lieh Chen ,  Lin-Kai Bu

发明人： Hsiao-Lan Su ,  Pen-Hsin Chen ,  Yu-Jui Chang ,  Ying-Lieh Chen ,  Lin-Kai Bu

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3688 ,  G09G2330/06

摘要： An interface circuit for data transmission and the method thereof is described. The interface circuit includes a transmitter providing data through first data signals during the data periods corresponding to rising and falling edges of a clock signal, a transition detection unit selectively asserting a detection signal in response to the number of the first data signals having transitions between every two adjacent data periods, a transition reduction unit generating second data signals by outputting the inverted and non-inverted first data signals respectively when the detection signal is asserted and de-asserted, and a receiver restoring the data from the second data signals and the detection signal.

摘要翻译： 描述了用于数据传输的接口电路及其方法。 接口电路包括：在与时钟信号的上升沿和下降沿相对应的数据周期期间通过第一数据信号提供数据的发射器，转换检测单元响应于第一数据信号的数量响应于每个 两个相邻数据周期，转换缩减单元，当检测信号被断言和解除断言时分别输出反相和非反相第一数据信号，并且接收机从第二数据信号恢复数据和检测 信号。

公开(公告)号：US20070222478A1

公开(公告)日：2007-09-27

申请号：US11417372

申请日：2006-05-03

申请人： Chien-Ru Chen ,  Ying-Lieh Chen ,  Lin-Kai Bu ,  Yu-Jui Chang

发明人： Chien-Ru Chen ,  Ying-Lieh Chen ,  Lin-Kai Bu ,  Yu-Jui Chang

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and a second ground terminal. An input terminal of the level shift unit is coupled to an output terminal of the input buffer unit. The voltage stabilizing capacitor is coupled between the first voltage source and the second ground terminal. When a state transition occurs in the level shift unit, the voltage stabilizing capacitor maintains a voltage difference between the output terminal of the input buffer unit and the second ground terminal.

摘要翻译： 提供电压电平移位电路。 电路包括输入缓冲单元，电平移位单元和稳压电容器。 输入缓冲器耦合在第一电压源和第一接地端子之间。 电平移位单元耦合在第二电压源和第二接地端子之间。 电平移位单元的输入端子耦合到输入缓冲器单元的输出端子。 稳压电容器耦合在第一电压源和第二接地端子之间。 当在电平移位单元中发生状态转移时，稳压电容器保持输入缓冲器单元的输出端子与第二接地端子之间的电压差。

公开(公告)号：US07449916B2

公开(公告)日：2008-11-11

申请号：US11417372

申请日：2006-05-03

申请人： Chien-Ru Chen ,  Ying-Lieh Chen ,  Lin-Kai Bu ,  Yu-Jui Chang

发明人： Chien-Ru Chen ,  Ying-Lieh Chen ,  Lin-Kai Bu ,  Yu-Jui Chang

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03L5/00

CPC分类号： H03K19/018528

摘要： A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and a second ground terminal. An input terminal of the level shift unit is coupled to an output terminal of the input buffer unit. The voltage stabilizing capacitor is coupled between the first voltage source and the second ground terminal. When a state transition occurs in the level shift unit, the voltage stabilizing capacitor maintains a voltage difference between the output terminal of the input buffer unit and the second ground terminal.

摘要翻译： 提供电压电平移位电路。 电路包括输入缓冲单元，电平移位单元和稳压电容器。 输入缓冲器耦合在第一电压源和第一接地端子之间。 电平移位单元耦合在第二电压源和第二接地端子之间。 电平移位单元的输入端子耦合到输入缓冲器单元的输出端子。 稳压电容器耦合在第一电压源和第二接地端子之间。 当在电平移位单元中发生状态转移时，稳压电容器保持输入缓冲器单元的输出端子与第二接地端子之间的电压差。

公开(公告)号：US07843420B2

公开(公告)日：2010-11-30

申请号：US11802979

申请日：2007-05-29

申请人： Chien-Ru Chen ,  Ying-Lieh Chen ,  Lin-Kai Bu

发明人： Chien-Ru Chen ,  Ying-Lieh Chen ,  Lin-Kai Bu

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/2092

摘要： A data transmitting method for inputting a data signal to an electronic device. The data signal includes first and second sets of data, and the electronic device includes first to fourth receiving units and corresponding first to fourth registers. The transmitting method includes the following steps. First, the first and second receiving units are disabled. Then, the first set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers during a first clock cycle of a clock signal. Thereafter, the second set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers while the first set of data stored in the third and fourth registers is inputted to the first and second registers during a second clock cycle of the clock signal.

摘要翻译： 一种用于向电子设备输入数据信号的数据发送方法。 数据信号包括第一和第二组数据，电子设备包括第一至第四接收单元和对应的第一至第四寄存器。 发送方法包括以下步骤。 首先，第一和第二接收单元被禁用。 然后，第一组数据通过第三和第四接收单元输入到电子设备，并且在时钟信号的第一时钟周期期间被存储在第三和第四寄存器中。 此后，第二组数据通过第三和第四接收单元输入到电子装置，并存储在第三和第四寄存器中，而存储在第三和第四寄存器中的第一组数据被输入到第一和第二寄存器 时钟信号的第二个时钟周期。

公开(公告)号：US07764259B2

公开(公告)日：2010-07-27

申请号：US11267289

申请日：2005-11-07

申请人： Tsung-Yu Wu ,  Ying-Lieh Chen ,  Lin-Kai Bu

发明人： Tsung-Yu Wu ,  Ying-Lieh Chen ,  Lin-Kai Bu

IPC分类号： G09G3/36

CPC分类号： G09G3/2096 ,  G09G2310/0275 ,  G09G2320/0223

摘要： A wire-on-array (WOA) flat panel display is provided. The wire-on-array (WOA) flat panel display is characterized in a plurality of high input impedance components between the flexible printed circuit (FPC) board and the corresponding source driver circuits. Each of the high input impedance components is able to receive gamma voltages with little input current and then transmit the gamma voltages to each of the source driver circuit for production of source voltages of little banding effect.

摘要翻译： 提供线阵列（WOA）平板显示器。 线对阵（WOA）平板显示器的特征在于柔性印刷电路板（FPC）板和对应的源极驱动电路之间的多个高输入阻抗分量。 每个高输入阻抗分量能够接收具有很小输入电流的伽马电压，然后将伽马电压传输到每个源极驱动电路，用于产生具有小带效应的源电压。

公开(公告)号：US20100045319A1

公开(公告)日：2010-02-25

申请号：US12609365

申请日：2009-10-30

申请人： Tzong-Yau Ku ,  Chien-Ru Chen ,  Chin-Tien Chang ,  Ying-Lieh Chen ,  Lin-Kai Bu

发明人： Tzong-Yau Ku ,  Chien-Ru Chen ,  Chin-Tien Chang ,  Ying-Lieh Chen ,  Lin-Kai Bu

IPC分类号： G01R1/06 ,  G01R31/02 ,  G01R31/26

CPC分类号： G01R31/2851 ,  G01R31/2831 ,  G01R31/2884

摘要： A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

摘要翻译： 提供晶片及其测试方法。 本发明利用第一组探针在第一芯片上执行高电压应力（HVS）测试，并且利用第二组探针在第二芯片上进行功能测试，其中高压应力测试的周期重叠 功能测试的一段时间，从而大大降低了晶片的测试时间。

公开(公告)号：US07609254B2

公开(公告)日：2009-10-27

申请号：US11055861

申请日：2005-02-11

申请人： Lin-Kai Bu ,  Ying-Lieh Chen ,  Tsung-Yu Wu ,  Hsin-Ta Lee ,  Bou Herng Hwe ,  Kun Hsiang Lo ,  Tzong Yau Ku

发明人： Lin-Kai Bu ,  Ying-Lieh Chen ,  Tsung-Yu Wu ,  Hsin-Ta Lee ,  Bou Herng Hwe ,  Kun Hsiang Lo ,  Tzong Yau Ku

IPC分类号： G09G5/00

CPC分类号： G09G3/3685 ,  G09G2330/06

摘要： The invention relates to a signal driving system for a display. The signal driving system comprises: a signal controller, a flexible connector and a plurality of driving devices. The signal controller is used to produce a first control signal. The flexible connector is connected to the signal controller, and used to receive the first control signal. One of the driving devices is connected to the flexible connector. The driving devices connect in cascade. Each driving device comprises a data input port, a data output port and a driving signal output port. The data input port receives the first control signal or a second control signal. The data output port outputs the second control signal. According to the first control signal or the second control signal, the driving signal output port transmits a driving signal. The signal driving system of the invention can make the data output port of the driving device transmit the second control signal to the next driving device. Therefore, the signal driving system of the invention can resolve the problem between different control signals of different circuit interfaces. Besides, the signal driving system of the invention has the advantage of processing the first control signal in the signal controller and transmitting the second control signal between the driving devices.

摘要翻译： 本发明涉及一种用于显示器的信号驱动系统。 信号驱动系统包括：信号控制器，柔性连接器和多个驱动装置。 信号控制器用于产生第一控制信号。 柔性连接器连接到信号控制器，用于接收第一控制信号。 其中一个驱动装置连接到柔性连接器。 驱动装置级联连接。 每个驱动装置包括数据输入端口，数据输出端口和驱动信号输出端口。 数据输入端口接收第一控制信号或第二控制信号。 数据输出端口输出第二个控制信号。 根据第一控制信号或第二控制信号，驱动信号输出端口发送驱动信号。 本发明的信号驱动系统可以使驱动装置的数据输出端口将第二控制信号发送到下一个驱动装置。 因此，本发明的信号驱动系统可以解决不同电路接口的不同控制信号之间的问题。 此外，本发明的信号驱动系统具有处理信号控制器中的第一控制信号并在驱动装置之间传输第二控制信号的优点。

公开(公告)号：US20090051844A1

公开(公告)日：2009-02-26

申请号：US12000397

申请日：2007-12-12

申请人： Chien-Chun Chen ,  Ying-Lieh Chen ,  Lin-Kai Bu

发明人： Chien-Chun Chen ,  Ying-Lieh Chen ,  Lin-Kai Bu

IPC分类号： G02F1/1333

CPC分类号： G09G3/36 ,  G09G3/006 ,  G09G3/3611 ,  G09G2330/08

摘要： A liquid crystal display (LCD) includes a controller, a source driver, first and second data lines and a data transmission path. The controller outputs first and second image data, and the source driver receives and outputs the first and second image data. The source driver includes first and second data channel circuits and a first repair channel circuit. The first and second data channel circuits respectively output first and second sub-pixel data. The first repair channel circuit is coupled to the controller to receive first repairing data. The first and second data lines are respectively coupled to the first and second data channel circuits to receive the first and second sub-pixel data. The data transmission path includes a redundant line, which is for coupling the first repair channel circuit to one of the first and second data lines, and interlaces with the first and second data lines.

摘要翻译： 液晶显示器（LCD）包括控制器，源驱动器，第一和第二数据线以及数据传输路径。 控制器输出第一和第二图像数据，并且源驱动器接收并输出第一和第二图像数据。 源驱动器包括第一和第二数据信道电路和第一修复信道电路。 第一和第二数据通道电路分别输出第一和第二子像素数据。 第一修复信道电路耦合到控制器以接收第一修复数据。 第一和第二数据线分别耦合到第一和第二数据通道电路以接收第一和第二子像素数据。 数据传输路径包括冗余线，其用于将第一修复信道电路耦合到第一和第二数据线之一，以及与第一和第二数据线交织。

公开(公告)号：US07327299B2

公开(公告)日：2008-02-05

申请号：US11467174

申请日：2006-08-25

申请人： Chen-Song Yen ,  Tsung-Yu Wu ,  Ying-Lieh Chen ,  Lin-Kai Bu

发明人： Chen-Song Yen ,  Tsung-Yu Wu ,  Ying-Lieh Chen ,  Lin-Kai Bu

IPC分类号： H03M1/66

CPC分类号： H03M1/68 ,  H03M1/76

摘要： A DAC has an N-bit R-string DAC section and an (M-N)-bit interpolation DAC section. The N-bit R-string DAC section has a plurality of resistors and a 2-of-N selector. The resistors are electrically connected in series to provide a plurality of voltage levels. The 2-of-N selector is coupled to the series-connected resistors, and is arranged to select two neighboring voltage levels according to an N-bit MSB subword. The (M-N)-bit interpolation DAC section is coupled to the N-bit R-string DAC section, and is arranged to interpolate an analog output signal from the two neighboring voltage levels according to an (M-N)-bit LSB subword.

摘要翻译： DAC具有N位R串DAC部分和（M-N）位插值DAC部分。 N位R串DAC部分具有多个电阻和2位N选择器。 电阻器串联电连接以提供多个电压电平。 2位N选择器耦合到串联电阻器，并且被布置为根据N位MSB子字选择两个相邻的电压电平。 （M-N）位插值DAC部分耦合到N位R串DAC部分，并且被配置为根据（M-N）位LSB子字来插入来自两个相邻电压电平的模拟输出信号。