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    Method for dicing semiconductor wafers
    1.
    发明授权
    Method for dicing semiconductor wafers 有权
    切割半导体晶片的方法

    公开(公告)号：US07183137B2

    公开(公告)日：2007-02-27

    申请号：US10725697

    申请日：2003-12-01

    申请人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/50 ,  H01L21/78

    CPC分类号： H01L21/78 ,  B28D5/00

    摘要： A method is disclosed for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure.

    摘要翻译： 公开了一种用于切割具有金刚石结构的基底材料的晶片的方法。 晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。 然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。

    Method for dicing semiconductor wafers
    2.
    发明授权
    Method for dicing semiconductor wafers 有权
    切割半导体晶片的方法

    公开(公告)号：US08288842B2

    公开(公告)日：2012-10-16

    申请号：US11655008

    申请日：2007-01-18

    申请人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L23/544 ,  H01L21/301

    CPC分类号： H01L21/78 ,  B28D5/00

    摘要： A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.

    摘要翻译： 一种方法提供用具有金刚石结构的具有基底材料的晶片切割。 晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。 然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。 制造具有一个或多个模具的晶片，其上的至少一个边缘与形成晶片的基底材料的金刚石结构的天然裂解方向成偏移角。 至少一个切割线具有一个或多个保护元件，用于在晶片沿着切割线切割时保护模具不受不期望的开裂。

    Method for dicing semiconductor wafers
    3.
    发明申请
    Method for dicing semiconductor wafers 有权
    切割半导体晶片的方法

    公开(公告)号：US20070117352A1

    公开(公告)日：2007-05-24

    申请号：US11655008

    申请日：2007-01-18

    申请人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  B28D5/00

    摘要： A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.

    摘要翻译： 一种方法提供用具有金刚石结构的具有基底材料的晶片切割。 晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。 然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。 制造具有一个或多个模具的晶片，其上的至少一个边缘与形成晶片的基底材料的金刚石结构的天然裂解方向成偏移角。 至少一个切割线具有一个或多个保护元件，用于在晶片沿着切割线切割时保护模具不受不期望的开裂。

    Relaxed silicon germanium substrate with low defect density
    6.
    发明授权
    Relaxed silicon germanium substrate with low defect density 有权
    具有低缺陷密度的松弛硅锗衬底

    公开(公告)号：US06878610B1

    公开(公告)日：2005-04-12

    申请号：US10228545

    申请日：2002-08-27

    申请人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

    发明人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

    IPC分类号： C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/36 ,  H01L21/84 ,  H01L29/10

    CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/324

    摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.

    摘要翻译： 已经开发了在松弛的低缺陷密度半导体合金层如SiGe上形成应变硅层的方法。 在本发明的第一实施例中，松散的低密度SiGe层在硅层上外延生长，硅层又位于下面的SiGe层上。 在覆盖SiGe层的外延生长期间，在下层硅层中形成缺陷，导致SiGe层所需的，松弛的和降低的缺陷密度。 第二个实施例的特征在于在松弛的SiGe层的生长期间执行的退火程序，导致附加的松弛和降低的缺陷密度，而第三实施例的特征在于在弛豫的SiGe层的外延生长之前对下面的硅层进行退火处理 允许为SiGe层实现优化的弛豫和缺陷密度。 在松弛的低缺陷密度SiGe层上获得应变硅层的能力允许在应变硅层的表面形成具有增强的载流子迁移率的器件，由于存在下面的，放松的， 低缺陷密度SiGe层。

    CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof
    10.
    发明授权
    CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof 有权
    在混合晶体取向上制造的CMOS逻辑门及其形成方法

    公开(公告)号：US07208815B2

    公开(公告)日：2007-04-24

    申请号：US10989080

    申请日：2004-11-15

    申请人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L29/04

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/7842 ,  H01L29/785

    摘要： In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

    摘要翻译： 在本发明的优选实施例中，描述了使用SOI和混合衬底取向形成CMOS器件的方法。 根据优选实施例，衬底可以具有多个晶体取向。 衬底中的一个逻辑门可以包括在一个晶体取向上的至少一个N-FET和另一个晶体取向上的至少一个P-FET。 衬底中的另一个逻辑门可以包括至少一个N-FET和至少一个相同取向的P-FET。 替代实施例还包括确定基板的优选解理平面并且考虑到它们各自优选的解理平面使基板相对于彼此定向。 在优选实施例中，解理平面不平行。