公开(公告)号：US20060008931A1

公开(公告)日：2006-01-12

申请号：US10888692

申请日：2004-07-09

申请人： Hsin-Hung Lee ,  Wei-Pang Huang ,  Chun-Hsiun Chen

发明人： Hsin-Hung Lee ,  Wei-Pang Huang ,  Chun-Hsiun Chen

IPC分类号： H01L21/00

CPC分类号： H01L27/3244 ,  H01L51/56

摘要： The present invention discloses a method for fabricating a pixel area of an electro-luminescent display device. At least one buffer layer is formed on a substrate. An etch stop layer is formed on the buffer layer. At least one intermediate layer is formed over the etch stop layer. The intermediate layer is etched to expose the etch stop layer, which has an etch rate substantially selective against that of the intermediate layer. The etch stop layer is etched to expose the buffer layer, which has an etch rate substantially selective against that of the etch stop layer, thereby improving an level uniformity of the exposed buffer layer.

摘要翻译： 本发明公开了一种制造电致发光显示装置的像素区域的方法。 在基板上形成至少一个缓冲层。 在缓冲层上形成蚀刻停止层。 在蚀刻停止层上形成至少一个中间层。 蚀刻中间层以暴露蚀刻停止层，蚀刻停止层的蚀刻速率基本上相对于中间层的蚀刻速率选择。 蚀刻停止层被蚀刻以暴露缓冲层，该缓冲层的蚀刻速率基本上相对于蚀刻停止层的蚀刻速率选择，从而提高了暴露的缓冲层的水平均匀性。

公开(公告)号：US07211456B2

公开(公告)日：2007-05-01

申请号：US10888692

申请日：2004-07-09

申请人： Hsin-Hung Lee ,  Wei-Pang Huang ,  Chun-Hsiun Chen

发明人： Hsin-Hung Lee ,  Wei-Pang Huang ,  Chun-Hsiun Chen

IPC分类号： H01L21/00

CPC分类号： H01L27/3244 ,  H01L51/56

摘要： The present invention discloses a method for fabricating a pixel area of an electro-luminescent display device. At least one buffer layer is formed on a substrate. An etch stop layer is formed on the buffer layer. At least one intermediate layer is formed over the etch stop layer. The intermediate layer is etched to expose the etch stop layer, which has an etch rate substantially selective against that of the intermediate layer. The etch stop layer is etched to expose the buffer layer, which has an etch rate substantially selective against that of the etch stop layer, thereby improving an level uniformity of the exposed buffer layer.

摘要翻译： 本发明公开了一种制造电致发光显示装置的像素区域的方法。 在基板上形成至少一个缓冲层。 在缓冲层上形成蚀刻停止层。 在蚀刻停止层上形成至少一个中间层。 蚀刻中间层以暴露蚀刻停止层，蚀刻停止层的蚀刻速率基本上相对于中间层的蚀刻速率选择。 蚀刻停止层被蚀刻以暴露缓冲层，该缓冲层的蚀刻速率基本上相对于蚀刻停止层的蚀刻速率选择，从而提高了暴露的缓冲层的水平均匀性。

公开(公告)号：US08553186B2

公开(公告)日：2013-10-08

申请号：US12571449

申请日：2009-10-01

申请人： An-Thung Cho ,  Chia-Tien Peng ,  Wan-Yi Liu ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： An-Thung Cho ,  Chia-Tien Peng ,  Wan-Yi Liu ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： G02F1/133

CPC分类号： H01L27/1214 ,  G02F1/1362 ,  G02F2001/13324 ,  G02F2202/36 ,  G09G3/3611 ,  G09G2330/02 ,  G09G2360/144 ,  H01L27/1259 ,  H01L29/78621

摘要： A display panel having a pixel region and a sensing region includes a first substrate, a second substrate and a display medium layer. A plurality of pixel structures and at least one photo-voltaic cell device are disposed on the first substrate. The pixel structures are arranged in the pixel region in array, and each of the pixel structures includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The photo-voltaic cell device disposed in the sensing region includes a doped semiconductor layer, a transparent electrode layer, a first type doped silicon-rich dielectric layer and a second type doped silicon-rich dielectric layer. The first type doped silicon-rich dielectric layer and the second type doped silicon-rich dielectric layer are disposed between the doped semiconductor layer and the transparent electrode layer. The display medium layer is disposed between the first substrate and the second substrate.

摘要翻译： 具有像素区域和感测区域的显示面板包括第一基板，第二基板和显示介质层。 多个像素结构和至少一个光电池单元设置在第一基板上。 像素结构被布置在阵列中的像素区域中，并且每个像素结构包括薄膜晶体管和电连接到薄膜晶体管的像素电极。 设置在感测区域中的光伏电池器件包括掺杂半导体层，透明电极层，第一类掺杂富硅介电层和第二掺杂富硅介电层。 第一类掺杂富硅介电层和第二掺杂富硅介电层设置在掺杂半导体层和透明电极层之间。 显示介质层设置在第一基板和第二基板之间。

公开(公告)号：US08093648B2

公开(公告)日：2012-01-10

申请号：US12501029

申请日：2009-07-10

申请人： An-Thung Cho ,  Chia-Tien Peng ,  Chih-Wei Chao ,  Wan-Yi Liu ,  Chia-Kai Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： An-Thung Cho ,  Chia-Tien Peng ,  Chih-Wei Chao ,  Wan-Yi Liu ,  Chia-Kai Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： A method for manufacturing a non-volatile memory and a structure thereof are provided. The manufacturing method comprises the following steps. Firstly, a substrate is provided. Next, a semiconductor layer is formed on the substrate. Then, a Si-rich dielectric layer is formed on the semiconductor layer. After that, a plurality of silicon nanocrystals is formed in the Si-rich dielectric layer by a laser annealing process to form a charge-storing dielectric layer. Last, a gate electrode is formed on the charge-storing dielectric layer.

摘要翻译： 提供了一种用于制造非易失性存储器的方法及其结构。 制造方法包括以下步骤。 首先，提供基板。 接下来，在基板上形成半导体层。 然后，在半导体层上形成富Si介电层。 之后，通过激光退火工艺在富Si介电层中形成多个硅纳米晶体，形成电荷存储电介质层。 最后，在电荷存储介质层上形成栅电极。

公开(公告)号：US20110116157A1

公开(公告)日：2011-05-19

申请号：US12699835

申请日：2010-02-03

申请人： Chuan-Sheng Wei ,  Sheng-Wen Huang ,  Pei-Ming Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： Chuan-Sheng Wei ,  Sheng-Wen Huang ,  Pei-Ming Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： G02F1/167

CPC分类号： G02F1/167 ,  G02F1/1362 ,  G02F2001/1672

摘要： An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.

公开(公告)号：US20100315580A1

公开(公告)日：2010-12-16

申请号：US12571449

申请日：2009-10-01

申请人： An-Thung Cho ,  Chia-Tien Peng ,  Wan-Yi Liu ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： An-Thung Cho ,  Chia-Tien Peng ,  Wan-Yi Liu ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： G02F1/133 ,  H01L21/77

CPC分类号： H01L27/1214 ,  G02F1/1362 ,  G02F2001/13324 ,  G02F2202/36 ,  G09G3/3611 ,  G09G2330/02 ,  G09G2360/144 ,  H01L27/1259 ,  H01L29/78621

摘要： A display panel having a pixel region and a sensing region includes a first substrate, a second substrate and a display medium layer. A plurality of pixel structures and at least one photo-voltaic cell device are disposed on the first substrate. The pixel structures are arranged in the pixel region in array, and each of the pixel structures includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The photo-voltaic cell device disposed in the sensing region includes a doped semiconductor layer, a transparent electrode layer, a first type doped silicon-rich dielectric layer and a second type doped silicon-rich dielectric layer. The first type doped silicon-rich dielectric layer and the second type doped silicon-rich dielectric layer are disposed between the doped semiconductor layer and the transparent electrode layer. The display medium layer is disposed between the first substrate and the second substrate.

摘要翻译： 具有像素区域和感测区域的显示面板包括第一基板，第二基板和显示介质层。 多个像素结构和至少一个光电池单元设置在第一基板上。 像素结构被布置在阵列中的像素区域中，并且每个像素结构包括薄膜晶体管和电连接到薄膜晶体管的像素电极。 设置在感测区域中的光伏电池器件包括掺杂半导体层，透明电极层，第一类掺杂富硅介电层和第二掺杂富硅介电层。 第一类掺杂富硅介电层和第二掺杂富硅介电层设置在掺杂半导体层和透明电极层之间。 显示介质层设置在第一基板和第二基板之间。

公开(公告)号：US20120241743A1

公开(公告)日：2012-09-27

申请号：US13489458

申请日：2012-06-06

申请人： Guang-Ren Shen ,  Pei-Ming Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： Guang-Ren Shen ,  Pei-Ming Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： H01L29/786

CPC分类号： H01L29/786

摘要： A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

摘要翻译： 提供薄膜晶体管（TFT）及其制造方法。 TFT包括沟道层，欧姆接触层，电介质层，源极，漏极，栅极和栅极绝缘层。 沟道层具有上表面和侧壁。 欧姆接触层设置在沟道层的上表面的一部分上。 电介质层设置在沟道层的侧壁上，并且不与欧姆接触层重叠。 源极和漏极设置在欧姆接触层和电介质层的部分上。 电介质层的一部分不被源极或漏极覆盖。 门在通道层的上方或下方。 栅极绝缘层设置在栅极和沟道层之间。

公开(公告)号：US08232147B2

公开(公告)日：2012-07-31

申请号：US12779955

申请日：2010-05-14

申请人： Guang-Ren Shen ,  Pei-Ming Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： Guang-Ren Shen ,  Pei-Ming Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： H01L29/786

CPC分类号： H01L29/786

摘要： A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

摘要翻译： 提供薄膜晶体管（TFT）及其制造方法。 TFT包括沟道层，欧姆接触层，电介质层，源极，漏极，栅极和栅极绝缘层。 沟道层具有上表面和侧壁。 欧姆接触层设置在沟道层的上表面的一部分上。 电介质层设置在沟道层的侧壁上，并且不与欧姆接触层重叠。 源极和漏极设置在欧姆接触层和电介质层的部分上。 电介质层的一部分不被源极或漏极覆盖。 门在通道层的上方或下方。 栅极绝缘层设置在栅极和沟道层之间。

公开(公告)号：US20100270551A1

公开(公告)日：2010-10-28

申请号：US12500609

申请日：2009-07-10

申请人： Chuan-Sheng Wei ,  Guang-Ren Shen ,  Chang-Yu Huang ,  Pei-Ming Chen ,  Sheng-Chao Liu ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： Chuan-Sheng Wei ,  Guang-Ren Shen ,  Chang-Yu Huang ,  Pei-Ming Chen ,  Sheng-Chao Liu ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L29/42384 ,  H01L29/41733 ,  H01L29/66765

摘要： A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.

摘要翻译： 提供底栅薄膜晶体管和有源阵列基板。 底栅薄膜晶体管包括栅极，栅极绝缘层，半导体层，多个源极和多个漏极。 栅极绝缘层设置在栅极上。 半导体层设置在栅极绝缘层上并位于栅极上方。 半导体层和栅极的面积比约为0.001〜0.9。 源极彼此电连接，并且漏极彼此电连接。

公开(公告)号：US08564584B2

公开(公告)日：2013-10-22

申请号：US12775443

申请日：2010-05-06

申请人： Chang-Yu Huang ,  Chuan-Sheng Wei ,  Pei-Ming Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： Chang-Yu Huang ,  Chuan-Sheng Wei ,  Pei-Ming Chen ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： G06F3/038

CPC分类号： G09G3/344 ,  G09G2300/08 ,  G09G2310/0267

摘要： An electrophoretic display with threshold voltage drift compensation functionality includes a gate driving circuit, a data driving circuit, a controller and a pixel array. The gate driving circuit provides plural gate signals according to a scan control signal. The data driving circuit provides plural data signals according to a data control signal. The controller is employed to provide the scan control signal and the data control signal. The pixel array is utilized for displaying images according to the gate signals and the data signals. Each of the gate signals includes a writing enable pulse for enabling write operations of the data signals during a writing period. And during a compensation period, each of the gate signals includes a compensation pulse for performing threshold voltage drift compensation operations on the data switches of the pixel array, and the data signals are set to hold a common voltage.

摘要翻译： 具有阈值电压漂移补偿功能的电泳显示器包括栅极驱动电路，数据驱动电路，控制器和像素阵列。 门驱动电路根据扫描控制信号提供多个门信号。 数据驱动电路根据数据控制信号提供多个数据信号。 控制器用于提供扫描控制信号和数据控制信号。 像素阵列用于根据门信号和数据信号显示图像。 每个门信号包括写使能脉冲，用于在写入周期期间实现数据信号的写操作。 并且在补偿期间，每个门信号包括用于对像素阵列的数据开关执行阈值电压漂移补偿操作的补偿脉冲，并且数据信号被设置为保持公共电压。