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    Nonvolatile memory structures and fabrication methods
    1.
    发明授权
    Nonvolatile memory structures and fabrication methods 有权

    公开(公告)号：US06643186B2

    公开(公告)日：2003-11-04

    申请号：US09974455

    申请日：2001-10-09

    申请人： Hsing Ti Tuan ,  Li-Chun Li

    发明人： Hsing Ti Tuan ,  Li-Chun Li

    IPC分类号： G11C1604

    CPC分类号： H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

    摘要： In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

    Nonvolatile memory structures and fabrication methods
    2.
    发明授权
    Nonvolatile memory structures and fabrication methods 有权

    公开(公告)号：US06617636B2

    公开(公告)日：2003-09-09

    申请号：US09952817

    申请日：2001-09-14

    申请人： Hsing Ti Tuan ,  Li-Chun Li ,  Thomas Tong-Long Chang

    发明人： Hsing Ti Tuan ,  Li-Chun Li ,  Thomas Tong-Long Chang

    IPC分类号： H01L29788

    CPC分类号： H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

    摘要： In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.