公开(公告)号：US06355524B1

公开(公告)日：2002-03-12

申请号：US09640139

申请日：2000-08-15

申请人： Hsing Ti Tuan ,  Li-Chun Li ,  Chung Wai Leung ,  Thomas Tong-Long Chang

发明人： Hsing Ti Tuan ,  Li-Chun Li ,  Chung Wai Leung ,  Thomas Tong-Long Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

摘要： In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

公开(公告)号：US06617636B2

公开(公告)日：2003-09-09

申请号：US09952817

申请日：2001-09-14

申请人： Hsing Ti Tuan ,  Li-Chun Li ,  Thomas Tong-Long Chang

发明人： Hsing Ti Tuan ,  Li-Chun Li ,  Thomas Tong-Long Chang

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

摘要： In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

公开(公告)号：US06700143B2

公开(公告)日：2004-03-02

申请号：US10165741

申请日：2002-06-06

申请人： Hsing Ti Tuan ,  Chung Wai Leung

发明人： Hsing Ti Tuan ,  Chung Wai Leung

IPC分类号： H01L31119

CPC分类号： H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/926

摘要： Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

摘要翻译： 形成在半导体衬底上的电路元件（例如晶体管栅极）在上覆电介质的机械或化学机械抛光期间被相邻的虚设结构保护。

公开(公告)号：US06559055B2

公开(公告)日：2003-05-06

申请号：US09846123

申请日：2001-04-30

申请人： Hsing Ti Tuan ,  Chung Wai Leung

发明人： Hsing Ti Tuan ,  Chung Wai Leung

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/926

摘要： Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

公开(公告)号：US06643186B2

公开(公告)日：2003-11-04

申请号：US09974455

申请日：2001-10-09

申请人： Hsing Ti Tuan ,  Li-Chun Li

发明人： Hsing Ti Tuan ,  Li-Chun Li

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

摘要： In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

公开(公告)号：US06757199B2

公开(公告)日：2004-06-29

申请号：US10434262

申请日：2003-05-07

申请人： Hsing Ti Tuan ,  Li-Chun Li

发明人： Hsing Ti Tuan ,  Li-Chun Li

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

摘要： A nonvolatile memory array can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells of the array in parallel.

摘要翻译： 非易失性存储器阵列可以被扇区擦除，或者可以执行芯片擦除操作以并行地擦除阵列的所有单元。