Method and apparatus for detecting inter-instruction data dependency

    公开(公告)号:US10684834B2

    公开(公告)日:2020-06-16

    申请号:US16360951

    申请日:2019-03-21

    Abstract: Embodiments of the present invention disclose a method and an apparatus for detecting inter-instruction data dependency. The method comprises: comparing a thread number corresponding to a historical access operation with a thread number corresponding to a write access operation, if the thread number corresponding to the write access operation is less than the thread number corresponding to the historical access operation, which indicates existence of data dependency for a to-be-detected instruction, terminating the detection; or comparing a thread number corresponding to a historical write access operation with a thread number corresponding to a read access operation, if the thread number corresponding to the read access operation is less than the thread number corresponding to the historical write access operation, which indicates existence of data dependency for the to-be-detected instruction, terminating the detection.

    Data Migration Method and Apparatus, and Processor
    3.
    发明申请
    Data Migration Method and Apparatus, and Processor 审中-公开
    数据迁移方法和装置以及处理器

    公开(公告)号:US20160306741A1

    公开(公告)日:2016-10-20

    申请号:US15197358

    申请日:2016-06-29

    Abstract: An on-chip memory in a many-core system is partitioned, and according to a frequency at which a processor core set in each on-chip partition accesses a virtual memory page in virtual memory space that is shared among multiple processes that belong to a same application program, data corresponding to the virtual memory page is moved to an on-chip memory partition in which a processor core set whose access frequency is high is located such that when the virtual memory page is subsequently accessed, a time delay caused by cross-partition access is reduced.

    Abstract translation: 多核系统中的片上存储器被分区,并且根据设置在每个片上分区中的处理器核心的频率访问虚拟存储器空间中的虚拟存储器页面,所述虚拟存储器页面在属于一个 相同的应用程序,对应于虚拟存储器页面的数据被移动到片上存储器分区,其中访问频率高的处理器核心集被定位成使得当虚拟存储器页被随后访问时,由交叉引起的时间延迟 减少了分区访问。

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