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公开(公告)号：US20190222436A1
公开(公告)日：2019-07-18
申请号：US16365863
申请日：2019-03-27
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xiaofei XU , Qingzhi LIU , Xiaojun ZHANG , Linchun WANG , Jingzhou YU
IPC: H04L12/28 , H04L12/931 , H04L12/24 , H04Q11/00
CPC classification number: H04L12/2885 , H04L12/00 , H04L41/0806 , H04L49/40 , H04Q11/0005 , H04Q11/0062 , H04Q2011/0052 , H04Q2011/0064
Abstract: The present disclosure relates to registration methods and devices. One example method includes obtaining, by a line card, line card information of the line card, the line card comprising a fabric interface chip optically interconnected to a switch fabric chip in at least one switch fabric card by using an optical fiber, and sending, by the line card, the line card information to the at least one switch fabric card through an optical interconnect path. The at least one switch fabric card registers the line card based on the line card information.
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公开(公告)号：US20210249747A1
公开(公告)日：2021-08-12
申请号：US17244741
申请日：2021-04-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Dajun ZANG , Cuicui WANG , Daochun MO , Yuchun LU , Linchun WANG
Abstract: Embodiments of this application provide a balance-unbalance conversion apparatus. The apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.
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Patent Agency Ranking
公开(公告)号：US20170109173A1
公开(公告)日：2017-04-20
申请号：US15391627
申请日：2016-12-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Nan LI , Linchun WANG
CPC classification number: G06F9/445 , G06F8/30 , G06F8/61 , G06F8/65 , G06F9/44 , H04L41/5054 , H04L41/5077 , H04L45/38 , H04L49/70
Abstract: A method for determining instruction sequences, a related device, and a system. A method for determining instruction sequences may include: acquiring a function identifier; and determining M1 instruction sequences used to implement a function identified by the function identifier, where each instruction sequence in the M1 instruction sequences includes a unique entry instruction, and each instruction sequence in the M1 instruction sequences includes a unique exit instruction, where M1 is a positive integer, and the M1 instruction sequences are instruction sequences for creating a network packet processing program used to process a network packet. Solutions of embodiments of the present disclosure are advantageous for improving an extent of matching between a packet forwarding device and an instruction sequence that is executed by the packet forwarding device and used to process a network packet, and reducing an amount of invalid code run by the packet forwarding device.
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公开(公告)号：US20210142837A1
公开(公告)日：2021-05-13
申请号：US17156938
申请日：2021-01-25
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Jingzhou YU , Linchun WANG
Abstract: This application relates to the field of storage technologies and discloses a content addressable memory, a data processing method, and a network device, to resolve a problem that an existing CAM has a relatively large area, and consumes relatively large power. The CAM includes bit units of M rows and N columns, each bit unit includes a first FeFET and a second FeFET, a source of the first FeFET is connected to a drain of the second FeFET, a source of the second FeFET is grounded, bit cells of a same column correspond to a same match line, and a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column. Bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row. The CAM may be applied to a network device such as a router.
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公开(公告)号：US20170046306A1
公开(公告)日：2017-02-16
申请号：US15337872
申请日：2016-10-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Nan LI , Linchun WANG , Hongfei CHEN
IPC: G06F15/80 , G06F9/38 , G06F15/163
CPC classification number: G06F15/80 , G06F9/38 , G06F9/3826 , G06F9/3828 , G06F13/1605 , G06F13/4031 , G06F15/163 , G06F15/17 , G06F15/825 , G06F2207/3868
Abstract: Disclosed are a data processing method, a processor, and a data processing device. The method comprises: an arbiter sends data D(a,1) to a first processing circuit; the first processing circuit processes the data D(a,1) to obtain data D(1,2), the first processing circuit being a processing circuit among m processing circuits; the first processing circuit sends the data D(1,2) to a second processing circuit; the second processing circuit to an mth processing circuit separately process the received data; and the arbiter receives data D(m,a) sent by the mth processing circuit. The processor further comprises an (m+1)th processing circuit. Each processing circuit in the first processing circuit to the (m+1)th processing circuit can receive first data to be processed sent by the arbiter, and process the first data to be processed. The scheme is helpful to improve efficiency of data processing.
Abstract translation: 公开了一种数据处理方法，处理器和数据处理装置。 该方法包括：仲裁器将数据D（a，1）发送到第一处理电路; 第一处理电路处理数据D（a，1）以获得数据D（1,2），第一处理电路是m个处理电路中的处理电路; 第一处理电路将数据D（1,2）发送到第二处理电路; 对第m处理电路的第二处理电路分别处理接收到的数据; 并且仲裁器接收由第m个处理电路发送的数据D（m，a）。 处理器还包括第（m + 1）个处理电路。 第（m + 1）处理电路的第一处理电路中的每个处理电路可以接收由仲裁器发送的待处理的第一数据，并处理第一待处理数据。 该方案有助于提高数据处理的效率。
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公开(公告)号：US20210336895A1
公开(公告)日：2021-10-28
申请号：US17369739
申请日：2021-07-07
Applicant: Huawei Technologies Co., Ltd.
Inventor： Zijian HE , Hui LU , Linchun WANG , Xingtao YAN , Yang LIU , Wenzong YANG , Jingzhou YU , Xiang YU
IPC: H04L12/801 , H04W72/14
Abstract: This application provides a data transmission method and a network device. The method includes: sending, by a first network device, request information to a second network device; receiving, by the first network device, grant information sent by the second network device, where the grant information includes a first sequence number; determining, by the first network device, a first credit limit based on the first sequence number, where the first credit limit is an amount of data that is allowed to be sent by the first network device in a packet-distributed load sharing manner; and sending, by the first network device, data to the second network device based on the first credit limit.
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公开(公告)号：US20200292770A1
公开(公告)日：2020-09-17
申请号：US16888121
申请日：2020-05-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Daochun MO , Qingzhi LIU , Xiaofei XU , Wenyang LEI , Chuang WANG , Linchun WANG
Abstract: This application discloses an optical backplane system, which includes a first upper-level optical interconnection module, a first lower-level optical interconnection module, and a second lower-level optical interconnection module. The first upper-level optical interconnection module includes M1 first interfaces and N1 second interfaces in connection relationships. The first lower-level optical interconnection module includes L1 third interfaces and K1 fourth interfaces in connection relationships. The second lower-level optical interconnection module includes L2 third interfaces and K2 fourth interfaces in connection relationships. The first upper-level optical interconnection module is connected to one of the L1 third interfaces of the first lower-level optical interconnection module by using one of the N1 second interfaces. The first upper-level optical interconnection module is connected to one of the L2 third interfaces of the second lower-level optical interconnection module by using another one of the N1 second interfaces.
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