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公开(公告)号：US10261694B2
公开(公告)日：2019-04-16
申请号：US15392856
申请日：2016-12-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xianfu Zhang
Abstract: Embodiments of the present invention provide a data storage method and system. The data storage method is applied to a data storage system, the data storage system includes a packet processing device, a processor, an off-chip memory, and a first counter corresponding to the off-chip memory, the off-chip memory is configured to store a count value of the first counter corresponding to the off-chip memory, and the packet processing device is configured to receive and process a service packet, count the service packet by using the first counter, and maintain an original address at which the count value of the first counter is stored in the off-chip memory. The method includes: scrambling, by the processor, the original address to obtain a scrambled address; and storing, by the processor, the count value of the first counter in a storage space corresponding to the scrambled address in the off-chip memory.
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公开(公告)号：US20170192675A1
公开(公告)日：2017-07-06
申请号：US15392856
申请日：2016-12-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xianfu Zhang
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0652 , G06F3/0653 , G06F3/0683 , G06F12/02 , G06F12/0207 , G06F12/0215 , G06F12/0607 , G06F12/1408 , G06F2212/1044
Abstract: Embodiments of the present invention provide a data storage method and system. The data storage method is applied to a data storage system, the data storage system includes a packet processing device, a processor, an off-chip memory, and a first counter corresponding to the off-chip memory, the off-chip memory is configured to store a count value of the first counter corresponding to the off-chip memory, and the packet processing device is configured to receive and process a service packet, count the service packet by using the first counter, and maintain an original address at which the count value of the first counter is stored in the off-chip memory. The method includes: scrambling, by the processor, the original address to obtain a scrambled address; and storing, by the processor, the count value of the first counter in a storage space corresponding to the scrambled address in the off-chip memory.
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Patent Agency Ranking
公开(公告)号：US11809730B2
公开(公告)日：2023-11-07
申请号：US17389461
申请日：2021-07-30
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xianfu Zhang , Zhengbo Wang
CPC classification number: G06F3/0647 , G06F3/0604 , G06F3/0653 , G06F3/0673
Abstract: A storage controller is coupled to a memory, and the memory includes a first storage area and a second storage area. The storage controller includes a data migration circuit and a data operation determining circuit. The data migration circuit is configured to generate a migration signal, to migrate data in the first storage area to the second storage area. In a process in which the data migration circuit migrates all the data in the first storage area to the second storage area, the data operation determining circuit is configured to: receive and monitor a data operation signal input to the memory, and output a data migration failure signal when detecting that the data operation signal is a data modify signal with respect to the first storage area.
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公开(公告)号：US20250055812A1
公开(公告)日：2025-02-13
申请号：US18928870
申请日：2024-10-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xianfu Zhang , Xinhui Li , Chao Lv
Abstract: A communication chip includes a switching (SW) die and a plurality of network processing (NP) dies. Any one of the plurality of NP dies is configured to: receive a first packet outside the communication chip through an external port, obtain destination information of the first packet, and send a second packet including the first packet and the destination information through an internal port. The destination information indicates a destination NP die of the first packet. The SW die is configured to: receive the second packet, and send the second packet to a first NP die in the plurality of NP dies based on the destination information. The first NP die is configured to: receive the second packet, and send the second packet outward through the external port.
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公开(公告)号：US10482027B2
公开(公告)日：2019-11-19
申请号：US15391112
申请日：2016-12-27
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xianfu Zhang , Qiang Wang
IPC: G06F12/08 , G06F12/0893 , G06F12/084 , G06F12/0871 , G06F9/50 , G06F12/0895
Abstract: This application relates to a cache management method and apparatus, so as to improve cache efficiency and reduce waste of cache resources. The cache management method provided in this application includes: after receiving a to-be-processed command, determining a quantity of cache units needed by the to-be-processed command; if the quantity of cache units needed by the to-be-processed command is one, searching for, based on a cache unit pair first state table, a pair of cache units in which only one cache unit is idle, and allocating the idle cache unit in the pair of cache units to the to-be-processed command; and if the quantity of cache units needed by the to-be-processed command is two, searching for and allocating, based on a cache unit pair second state table in a clock cycle, a pair of cache units in which two cache units are both idle to the to-be-processed command.
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公开(公告)号：US10430344B2
公开(公告)日：2019-10-01
申请号：US15392317
申请日：2016-12-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xianfu Zhang , Qiang Wang
IPC: G06F12/00 , G06F12/0891 , G06F12/08 , G06F12/0815 , G06F12/121 , G06F11/10
Abstract: The present invention provides a memory resource management method and apparatus. The method includes: first, determining a recyclable cache unit according to first indication information and second indication information that correspond to each cache unit, where the first indication information and the second indication information both include at least one bit, the first indication information indicates whether the cache unit is occupied, and the second indication information indicates a quantity of cache unit recycling periods for which the cache unit has been occupied; and then, recycling the recyclable cache unit. A quantity of cache unit recycling periods is set, and when a time for which a cache unit has been occupied reaches the preset quantity of cache unit recycling periods, the cache unit is forcibly recycled, thereby effectively improving cache unit utilization and improving system bandwidth utilization.
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公开(公告)号：US20170185522A1
公开(公告)日：2017-06-29
申请号：US15392317
申请日：2016-12-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xianfu Zhang , Qiang Wang
IPC: G06F12/0891 , G06F12/0815
Abstract: The present invention provides a memory resource management method and apparatus. The method includes: first, determining a recyclable cache unit according to first indication information and second indication information that correspond to each cache unit, where the first indication information and the second indication information both include at least one bit, the first indication information indicates whether the cache unit is occupied, and the second indication information indicates a quantity of cache unit recycling periods for which the cache unit has been occupied; and then, recycling the recyclable cache unit. A quantity of cache unit recycling periods is set, and when a time for which a cache unit has been occupied reaches the preset quantity of cache unit recycling periods, the cache unit is forcibly recycled, thereby effectively improving cache unit utilization and improving system bandwidth utilization.
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